Octal and Quad SPI Flash Controller and PHY for SoC Designs | Cadence IP

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Octal and Quad SPI Flash Controller and PHY


  • FlexibilitySeveral SPI protocols with single IP allows for single system-on-chip (SoC) design for several derivatives (low/mid/high-end)
  • SimplicityUsing soft PHY simplifies SoC timing design
  • High performanceSupports maximum Octal SPI data rates and XIP

Flash memory is demanding ever higher transfer rates and lower latency, and is utilized frequently in computers and electronic devices found in automotive, IoT, drones, connected home, and other emerging applications. Expanding the flash Serial Peripheral Interface (SPI) accesses from the current four I/Os (Quad SPI) to eight I/Os (Octal SPI) increases the Serial NOR Flash throughput and provides a more efficient solution for emerging applications, while providing backwards compatibility with support for single, dual, quad, or octal I/O interfaces.

The Cadence® Controller and PHY IP for Quad Serial-Peripheral Interface (QSPI) improved performance enables Octal SPI designs to not only utilize continuous mode or Execute in Place (XIP) with more efficiency. It also shortens the time, allowing overall acceleration of the entire system performance. The integration of the soft PHY enables the highest speed clock rates and at the same time the need for a reference clock at four times (4X) evaporates. That allows the creation of simplified SoC designs, complexity reduction of additional clock domains, and power reduction used by the OSPI bus.

Flexibility encompassed as several SPI protocols with single IP, presence of soft PHY with portability and low power are among benefits of this Controller and PHY IP. The list is long and with every single design installed in cars, smart homes ecosystems, and mobile devices, it becomes clear that the only way to make it happen is with IP ready to handle the heat.


  • Local SRAM of configurable size to reduce AHB overhead and buffer Flash data during indirect transfers
  • Optional DMA peripheral interface to communicate indirect mode status with external DMA
  • Up to 133MHz SDR or 80MHz DDR for Quad SPI devices
  • Independent reference clock to decouple AHB clock from SPI clock–allows for slow system clocks
  • Memory mapped ‘direct’ mode for XIP
  • Support BOOT mode and XIP (eXecute In Place)


  • Host Controller IP for xSPI
  • Controller and PHY IP for Octal SPI Flash
  • Controller and PHY IP for Quad Serial-Peripheral Interface (QSPI)
  • Controller IP for Quad Serial-Peripheral Interface