Octal and Quad SPI Flash Controller and PHY for SoC Designs | Cadence IP

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Octal and Quad SPI Flash Controller and PHY

Flash memory is demanding ever higher transfer rates and lower latency, and is utilized frequently in computers and electronic devices found in Automotive, IoT, Drones, Connected Home, and other emerging applications. Expanding the flash Serial Peripheral Interface (SPI) accesses from the current 4 I/Os (Quad SPI) to 8 I/Os (Octal SPI) increases the Serial NOR Flash throughput and provides a more efficient solution for emerging applications, while providing backwards compatibility with support for single, dual, quad, or octal I/O interfaces.


  • Flexibility – several SPI protocols with single IP
  • Simplicity - using Soft PHY simplifies SoC timing design
  • Choice - between Quad or Octal interfaces

Cadence Octal SPI Flash Controller improved performance enables Octal SPI designs to not only utilize continuous mode or Execute in Place (XIP) with more efficiency. It also shortens the time, allowing overall acceleration of the entire system performance. The integration of the soft PHY enables the highest speed clock rates and at the same time the need for a reference clock at 4 times (4x) evaporates. That allows the creation of simplified SoC designs, complexity reduction of additional clock domains, and power reduction used by the OSPI bus.

Flexibility encompassed as several SPI protocols with single IP, presence of soft PHY with portability and low power are among benefits of this Cadence IP. The list is long and with every single design installed in cars, smart homes ecosystems, and mobile devices, it becomes clear that the only way to make it happen is with IP ready to handle the heat.


  • Memory mapped ‘direct’ mode for XIP
  • Software triggered ‘indirect’ mode for low latency data transfers
  • DMA peripheral interface for indirect mode
  • Up to 200MHz DDR (with DQS) for Octal SPI devices
  • Up to 133MHz SDR or 80MHz DDR for Quad SPI devices
  • Support BOOT mode and XIP (eXecute In Place)
  • Support for single, dual, quad, octal I/O instructions
  • Independent reference clock to decouple AHB clock from SPI clock – allows slow system clocks


Controller and PHY IP for Octal SPI Flash

Controller and PHY IP for Quad Serial-Peripheral Interface (QSPI)

Controller IP for Quad Serial-Peripheral Interface