NAND Flash PHY IP for SoC Designs | Cadence IP


The Cadence NAND Flash PHY IP is an all-digital, soft PHY design that uses a DFI 2.0 interface modified for NAND. Compatible with all major NAND devices, the Cadence NAND Flash PHY IP provides support for legacy asynchronous devices within a single interface. The IP also supports ONFI 4, 3, 2, 1 and Toggle 2, 1 interfaces. Our NAND Flash PHY IP has a register interface for setup, configuration, and calibration.

Architected to quickly and easily integrate into any system on chip (SoC), the Cadence NAND Flash PHY IP connects seamlessly to our NAND Flash Controller IP or to third-party NAND Flash controllers that support a modified DFI 2.0 interface. Implemented for the most popular foundries and processes, it is a cost-effective, low-power solution for demanding applications. If you are an SoC integrator, you will find that our advanced capabilities and support exceed the requirements of high-performance designs and implementations. The Cadence NAND Flash PHY IP offers speeds up to 266MHz, while it can also operate at up to 400MHz with ONFI 4 being supported. And most importantly, the structure allows easy accommodation of future clock rate increases.

Take advantage of an automated design flow with advanced synthesis and static timing analysis (STA) scripts that permit register-transfer level (RTL)-to-placed gates in an easy manner.

Based on our proven DDR DRAM PHY design, our NAND Flash PHY IP is silicon-proven and has been extensively validated with multiple hardware platforms.


  • High-performance design with small area and low-power operation
  • Wide standard support for system flexibility
  • Based on the proven Cadence DDR PHY IP designs


  • NAND Flash PHY IP supports ONFI 1, 2, 3, and Toggle 1, 2
  • NAND Flash ONFI 4 PHY IP supports ONFI 1, 2, 3, 4, and Toggle 1, 2