NAND Flash Host Controller IP for SoC Designs | Cadence IP

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Host Controller IP for NAND Flash


  • Highly-integrated IP offering—speeds system integration and reduces design costs
  • Command and Data DMA—reduces software overhead
  • Wide support of standards enables system flexibility

The Cadence® Controller IP for NAND Flash provides all the necessary logic required to efficiently control all major NAND Flash devices. 

Supporting all major NAND standards, and providing early support for emerging standards, our Controller IP for NAND Flash has many configurable features and input parameters to customize the controller for the specific needs of any application. Support for widely used legacy interfaces is also available. 

Our Controller IP for NAND Flash is architected to quickly and easily integrate into any system on chip (SoC) and, when used with the Cadence PHY IP for NAND Flash, connects seamlessly from the SoC bus to the I/O drivers in the ASIC I/O pad ring. 

The Cadence Controller IP for NAND Flash is architected to quickly and easily integrate into any SoC through the industry-standard ARM® AMBA®4 AXI as a high-speed master interface and AMBA APB or AXI-Lite as register interfaces.

Silicon proven, our Controller IP for NAND Flash has been extensively validated in many processes and with multiple hardware platforms.


  • Pipelined read-ahead and write commands for enhanced read and write throughput
  • Single-level cell (SLC) and multi-level cell (MLC) support, including for boot operation
  • Support for all Flash vendors
  • Supports pages sizes from 256B to 16kB
  • Advanced ECC supports different parallel factors to achieve maximum throughput
  • Slave DMA interface directly to data buffer
  • Support for high-speed memories (up to 800MT/s)
  • Command DMA supports 32-bit or 64-bit addressing
  • Support for multi-LUN modes
  • 8-bit and 16-bit Flash devices support