LPDDR5 PHY IP Solution | Cadence IPLPDDR5 PHY IP Solution | Cadence IPLPDDR5 PHY IP Solution | Cadence IP

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LPDDR5 PHY IP Solution

Benefits

  • Silicon-proven IP reduces implementation risks

  • 7nm implementation for best power and performance

  • Lowest latency for data-intensive applications

  • Highest data rates with detailed system guidelines for demanding applications

  • Maximum system margin with advanced clocking and I/O architectures optimize power and area

LPDDR5 PHY IP

Today’s consumers generate and consume large volumes of data and video, exploding the need for data-intensive processing requiring high memory bandwidth. The Cadence® Denali® Gen2 PHY IP for LPDDR5/4/4x is a family of high-speed on-chip memory interface IP satisfying high-performance requirements with products that are optimized for each application's needs.

LPDDR5 PHY IP Write Eye Diagram at 5500Mbps

The LPDDR5 PHY IP is comprised of architectural improvements to its highly successful predecessor, achieving breakthrough performance, lower power consumption, and smaller overall area. The application-optimized LPDDR5 PHY IP can achieve speeds up to 5500Mbps. Low-power features include the addition of a VDD low-power idle state in the PHY and power efficient clocking during low-speed operation for longer battery life and greener operation. Redesigned I/O elements reduce overall area by up to 20%.

The LPDDR5 PHY IP is developed by experienced teams with industry-leading domain expertise and extensively validated with multiple hardware platforms. It is engineered to quickly and easily integrate into an SoC and is verified with the Denali Controller IP for LPDDR5/4/4X as part of a complete memory subsystem solution. The LPDDR5 PHY IP is designed to connect seamlessly and work with a third-party DFI-compliant memory controller.

Integrated Solution

When implemented as part of a single-vendor solution, the LPDDR5 PHY IP reduces integration challenges between the PHY, controller, and the rest of the SoC. Cadence deploys proven design techniques that reuse technology from Cadence’s silicon-proven DDR designs, lowering customers’ risk when implementing LPDDR5 interfaces. The LPDDR5/4/4X controller is based on the industry-leading Denali DDR controller heritage, and customers benefit from a full set of popular features for memory interfaces, such as support for Arm AMBA AXI buses and reliability features like in-line error correcting codes. Industry-leading verification IP is available to speed SoC-level verification.

LPDDR5 PHY IP Silicon Testing

Key Features

• Application-optimized configurations for fast time to delivery and lower risk
• Low-power VDD idle, VDD light sleep, and power-efficient clocking in low-speed modes
• Memory controller interface complies with DFI 5.0 standard
• I/O pads with impedance calibration logic and data retention capability

Cadence’s demonstration of LPDDR5 design IP that is silicon proven in TSMC 7nm FinFET process technology enables many future chips that will embrace the LPDDR5 technology. TSMC’s 7nm process technology continues to be the 7nm process of choice for advanced designs, including mobile and automotive applications that LPDDR5 primarily focuses on.

– Suk Lee, senior director of Design Infrastructure Management Division, TSMC

Modern automotive and mobile applications require fast memory access to keep up with the rapid pace of industry innovation. The announcement of LPDDR5 design IP supporting AMBA protocols underscores our ongoing collaboration with Cadence and enables the ecosystem to deliver next-generation Arm-based processors uniquely designed for client and automotive applications.

– Francisco Socal, senior product manager, Architecture and Technology Group, Arm

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