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HBM PHY and Controller IP


  • Derived from Cadence’s silicon-proven DDR and LPDDR IP designs
  • Achieves highest data rates with detailed system guidelines
  • Delivers maximum system margin with advanced clocking and I/O architectures

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The PHY IP for HBM2E/2 is comprised of architectural improvements drawn from previous-generation DDR5 and LPDDR4 PHYs, achieving breakthrough performance, low energy per bit, and low area relative to the bandwidth provided. The PHY IP for HBM2E/2 was developed by experienced teams with industry-leading domain expertise and extensively validated with multiple hardware platforms. It is engineered to quickly and easily integrate into SoCs, and is verified with the Denali Controller IP for HBM2E/2 as part of a complete memory subsystem solution.

HBM2 PHY IP Block Diagram

Artificial intelligence (AI), high-performance computing (HPC), image processing, and autonomous driving applications generate and consume large volumes of data and require very high memory bandwidth. The Cadence® Denali® PHY IP for HBM2E/2 for the Samsung 8LPP Process is an ideal solution for meeting these high-performance applications.


  • Lowest latency for data-intensive applications
  • Advanced clocking architecture minimizes clock jitter
  • Highest data rates with high-resolution delay adjust
  • Designed for optimized interposer routing
  • Memory controller interface uses DFI 4.0-like standard
  • DFI PHY Independent Mode for initialization and training
  • IEEE 1500 interface, BIST module, and loop-back function
  • Debug and bring-up software


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