GDDR6 IP for SoC Designs | Cadence IP

Home: IP Portfolio > Design IP > Denali Memory Interface IP > DDR IP > GDDR6 IP Solution

GDDR6 IP Solution

Benefits

  • Leverages design technology from Cadence’s silicon-proven DDR and high-speed SerDes designs, resulting in lower risk when implementing GDDR6
  • Low BER reduces retries on the memory bus, providing greater bandwidth and lower maximum latency
  • Wide design margin allows users to implement GDDR6 on PCBs with common materials such as FR4, reducing the cost of GDDR6 deployment
  • Available GDDR6 reference design allows users to replicate Cadence’s test-chip results in their own products
  • Industry-leading VIP, now extended with GDDR6 support, enables robust verification of the GDDR6 interface in context of the full SoC

Integrated Solution

The Cadence® IP Solution for GDDR6 consists of PHY, controller, and Verification IP (VIP) serving very-high-bandwidth memory applications. With PHY availability in 7nm semiconductor process technology, the solution is ideal for applications including machine learning, AI, cryptocurrency mining, graphics, automated driving, ADAS, and high-performance computing (HPC).

Cadence’s tapeout of GDDR6 IP in Samsung Foundry’s 7LPP process is a milestone in our successful collaboration to deliver a superior GDDR6 solution to our mutual customers.

– Jaehong Park, senior vice president of Foundry Design Service Team, Samsung Electronics

Until now, GDDR memories have been predominantly used for graphics applications, with limited use elsewhere. As a result, DDR4 and LPDDR4 have been the memories of choice for early adopters addressing high-bandwidth memory applications. GDDR6 offers 5X faster memory bandwidth than the fastest speed of DDR4 at a moderate cost, making it ideal for such applications.

However, design at GDDR6 data rates requires new architecture and techniques. Cadence is poised to address this market need with robust GDDR6 IP, based on its industry-leading Denali® DDR controller and silicon-proven high-speed SerDes technology and verified against Cadence’s verification IP for GDDR6.

Simulation of GDDR6 16G data eye with channel effects

Cadence’s new GDDR6 IP allows up to 16Gb/sec bandwidth per pin, or over 500Gb/sec peak bandwidth between the SoC and each GDDR6 memory die. This enables users to design high-memory-bandwidth GDDR6 interfaces with a lower number of DRAM dies than is possible with DDR4, reducing both PCB area and packaging pins. Cadence’s unique, single-vendor GDDR6 IP solution speeds integration and reduces interoperability risk. In addition, customers benefit from reduced risk of interoperability issues between their SoC and memory devices because the Cadence GDDR6 IP was developed in close collaboration with Samsung, the leading DRAM provider.

Cadence’s GDDR6 controller relies heavily on a strong history of DRAM controllers and is based on our DDRx and LPDDRx controllers. Integrating popular and silicon-proven DRAM controller features like Arm AMBA AXI ports, multiport arbitration, a priority-based and bandwidth-based reordering queue, RAS features, memory BIST, and in-line ECC, the goal of Cadence’s GDDR6 controller is to give the user the same facilities they are used to with DDR and LPDDR controllers while connecting to GDDR6.

Cadence’s GDDR6 controller is pipelined correctly and geared for implementation to connect to a DFI interface modified for GDDR6 with low latency, while closing timing at 16G speeds and above in 7nm technologies.

Rapid System Bring-Up

With other solutions, system bring-up is gated by the need for customers to write their own firmware U-Boot code in order for the SoC’s CPU to boot DRAM. This can result in the long-awaited first silicon sitting in the lab for days or weeks—after all, nothing works until the DRAM works.

However, with the Cadence GDDR6 IP bring-up approach, users can:

  • Directly access DRAM controller and PHY registers through JTAG
  • Bring up DRAM interface fast—typically in one day
  • Use software that allows 2D eye shmoo on any pin—without probing
  • Easily port DRAM parameters into chip-level firmware
  • Allow Cadence staff to remotely and securely debug DRAM interface issues

Generate 2D eye shmoo on any pin (LPDDR4 example)

We use Cadence LPDDR4 IP in our fast turnaround video solution for digital video consumer applications, such as cameras and TVs. We succeeded in bringing up our LPDDR4 memory subsystem with the help of Cadence DDR IP bring-up software within an hour of receiving the chip back.  

– Japanese SoC vendor

We used the DDR IP bring-up software to try various IP settings and determine the optimal DDR system initialization code to be used in the firmware.
– US-based system OEM

We used Cadence bring-up software enabled on windows laptop and were able to perform training and BIST to successfully write/read/compare DDR memory. Pretty good success for just over an hour of work.
– US-based storage OEM

 

Request Further Information