DDR PHY IP for SoC Designs | Cadence IPDDR PHY IP for SoC Designs | Cadence IPDDR PHY IP for SoC Designs | Cadence IP


Today’s consumers are generating and consuming large volumes of data and video, exploding the required capacity and bandwidth for device memory. Cadence is leading the way, providing the Cadence® Denali® DDR IP family of high-speed, on-chip interface IP with the bandwidth necessary to support these applications. The DDR PHY IP provides low latency and up to 3200Mbps throughput, while balancing power consumption and minimizing area.

The DDR PHY IP is engineered to quickly and easily integrate into any system-on-chip (SoC), and is verified with the Denali DDR Controller IP as part of a complete memory subsystem solution. The DDR PHY IP is designed to connect seamlessly and work with third-party, DFI-compliant memory controllers.

The DDR PHY IP is developed and validated to reduce risk for the customer so that their SoC will work right the first time. Developed for and available early in the life cycle of the most advanced semiconductor process nodes, the DDR PHY IP is designed to be robust under varying noise conditions and to have interoperability with various supplier memory chips.

Product Options

The DDR PHY IP is available as products optimized for specific applications like GDDR6, DDR4, DDR3, and DDR3L. It is also available as products optimized for LPDDR4 and LPDDR3, with many configuration options to select desired features and integration aspects.

DDR PHY Block Diagram


  • Lowest-latency for data-intensive applications

  • Highest data rates with detailed system guidelines

  • Maximum system margin with advanced clocking

Key Features

  • GDDR6 Support
  • LPDDR4/3 DDR4/3/3L training with write-leveling and data-eye training

  • Optional clock gating available for low-power control
  • Memory controller interface complies with DFI standards 4.0 or 3.1
  • Internal and external datapath loop-back modes
  • I/O pads with impedance calibration logic and data retention capability
  • Multiple PLLs for maximum system margin
  • Programmable clock delay (PVT compensated) on read
    and write datapaths for DQS alignment
  • Per-bit deskew on read and write datapath