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DDR/LPDDR Controller IP

The Cadence® Denali® DDR Controller IP technology continues to advance since its inception well over a decade ago. Since that time the Denali DDR controller IP has been used in countless diverse applications delivering superior data throughput and continuing to incorporate new innovative capabilities that provide DDR DRAM subsystem designers significant value. 

DDR Controller performance continues to be important with more new applications demanding higher throughput, improved power management, and better reliability. For DDR DRAM subsystem designers who need DDR Controller IP, the Denali DDR Controller IP offers several capabilities to help better manage DDR subsystem such as DRAM power management advances and meaningful innovations in DDR subsystem management. 

The Denali DDR Controller delivers a wide array of capabilities to address emerging DDR DRAM subsystem Reliability, Availability and Serviceability (RAS) requirements. The controller includes ECC and other vital error detection and error prevention capabilities such as parity and system data scrubbing. 

These innovations are in response to industry demands and emerging market needs. The Cadence Denali DDR Controller IP continues to evolve and meet or exceed DDR DRAM subsystem designer requirements.

DDR Controller Block Diagram


  • Configurable to meet specific data traffic profiles

  • Optimized low latency for data-intensive applications

  • Future-proof system design for emerging DDR standards

Key Features

  • GDDR6 and HBM2E/2 Support
  • DDR5/4/3 in-line ECC
  • Supports advanced RAS features including SEC/DED ECC, error scrubbing, parity, etc.
  • Compliant to LPDDR5/4x/4/3 and DDR4/3/3L protocol memories
  • Priority per command on Arm® AMBA® 4 AXI, AMBA 3 AXI
  • Single and multi-port host interface options
  • QoS features allow command prioritization on Arm AMBA 4 AXI interfaces
  • Flexible paging policy including auto-precharge-per-command
  • Silicon proven and shipping in volume