USB 2.0 PHY for SoC Designs | Cadence IPUSB 2.0 PHY for SoC Designs | Cadence IPUSB 2.0 PHY for SoC Designs | Cadence IP

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The Cadence® USB 2.0 OTG PHY IP is a hard PHY macro consisting of a single USB 2.0 PHY core. This IP is designed to the USB 2.0 specification, and operates at High Speed (480Mbps), Full Speed (12Mbps), and Low Speed (1.5Mbps). The USB 2.0 core complies with the UTMI v1.05 specification.

Architected to quickly and easily integrate into any system-on-chip (SoC), the Cadence USB 2.0 OTG PHY IP connects seamlessly to a Cadence or third-party UTMI-compliant controller. The IP provides you with a cost-effective, low-power solution for demanding applications. It offers SoC integrators the advanced capabilities and support that exceed the requirements of high-performance designs and implementations.

The Cadence USB 2.0 OTG IP is silicon-proven, and has been extensively validated with multiple hardware platforms.


  • Compliant with USB 2.0, USB OTG specifications
  • Supports Battery Charge v1.2 specification
  • Complies with UTMI+ / FsLsSerialMode Interface


USB 2.0 OTG PHY Block Diagram