16G Multi-Protocol PHY for SoC Designs | Cadence IP16G Multi-Protocol PHY for SoC Designs | Cadence IP16G Multi-Protocol PHY for SoC Designs | Cadence IP

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16G Multi-Protocol PHY

The Cadence® 16G Multi-Link and Multi-Protocol PHY is a silicon-proven, high-end SerDes operating at speeds from 1.25Gbps to 16Gbps. It features Long Reach equalization capability at very low active and standby power. This SerDes offers ultra-low exit latency for time-critical application. A great number of protocols are supported simultaneously such as PCIe 4.0, USB 3.1, Ethernet 100G, 40G, 10G, and 1G,SFI/XFI, SATA, Q/SGMII, just to name a few.

16G Multi-Link and Multi-Protocol PHY allows great flexibility to mix and match protocols within the same macro. A multitude of test features are embedded and easily accessible by the end-user. Finally, the user-friendly graphical interface provides easy access to embedded bit-error-rate (BER) and Pattern testers and monitors to measure the link performance in real time.

Multi-Protocol SerDes (=PMA) Block Diagram - 
Example: Multi-link Support

Ethernet Protocols

  • 100GBASE-CR10 / R
  • 40GBASE-KR4/CR4
  • 10 and 12.5GBASE-KR
  • CEI-11G / 6G
  •  XFI/SFI (SFF-8431)
  • XAUI
  • 1 Gigabit Ethernet

PCIe Protocols

  • PCIe 4.0, 3.0, 2.0, 1.0

USB Protocols

  • USB 3.1 (Gen 1 and 2), a.k.a. USB SuperspeedPlus (10G)
  • USB 2.0

Key Features

  • Multi-Link, Multi-Protocol SerDes
  • Long reach equalization capability
  • Ultra low power and low latency