16G Multi-Protocol PHY for SoC Designs | Cadence IP16G Multi-Protocol PHY for SoC Designs | Cadence IP16G Multi-Protocol PHY for SoC Designs | Cadence IP

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16G Multi-Protocol PHY

The Cadence® 16G Multi-Link and Multi-Protocol PHY is a silicon-proven, high-end SerDes operating at speeds from 1.25Gbps to 16Gbps. It features long-reach equalization capability at very low active and standby power. This SerDes offers ultra-low exit latency for time-critical applications. A great number of protocols are supported simultaneously such as PCIe 4.0, 10G-KR, and QSGMII/SGMII, just to name a few.

The 16G Multi-Link and Multi-Protocol PHY allows great flexibility to mix and match protocols within the same macro. A multitude of test features are embedded and easily accessible by the end user. Finally, the user-friendly graphical interface provides easy access to embedded bit-error-rate (BER) and pattern testers and monitors to measure the link performance in real time.​

Multi-Protocol SerDes (=PMA) Block Diagram - 
Example: Multi-link Support

Benefits

  • High-performance: Single macro supports max 16Gbps with up to 16 lanes for long-reach applications

  • Mature and silicon proven: Compliance proven, customer SoCs in volume production

  • Low risk: Fully validated by Cadence’s rigorous IP qualification process and system stress tests

  • Ease of use: Fully verified pre-integrated IP delivery, with package and signal integrity support and firmware for rapid bring-up

Key Features

  • Wide range of protocols that support networking, HPC, and applications

  • Low-latency, long-reach and low-power modes

  • Multi-Link PHY—mix protocols within the same macro

  • EyeSurf —non-destructive on-chip oscilloscope

  • Extensive set of isolation, test modes, and loop-backs including APB and JTAG

  • Supports 16-bit, 20-bit, and 32-bit PIPE and non-PIPE interfaces

  • Selectable serial pin polarity reversal for both transmit and receive paths