10G Multi-Protocol SerDes for SoC Designs | Cadence IP

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10G Multi-Protocol PHY

The Cadence® 10G Multi-Protocol PHY is a silicon-proven design that implements a multi-lane PHY architecture to support data rates from 1.25Gbps to 10.40Gbps per lane. It features Long Reach equalization capability at very low active and standby power. This Serdes offers ultra-low exit latency (L1.1 and L1.2) for time-critical application. 

The Cadence 10G Multi-Protocol PHY IP allows the user to mix and match protocols within the same macro. A multitude of test features are embedded and easily accessible through a user-friendly graphical interface. The Cadence 10G Multi-Protocol PHY IP is designed with a lane-based architecture, providing greater control over floorplanning, placement, packaging, and I/O integration than other hard PHY solutions, while maintaining reliability and ease-of-use.


Multi-Protocol SerDes (=PMA) Block Diagram - Overview


  • CPRI

  • XAUI


  • 1GE (1000BASE-KX/BX)

Key Features

  • Multi-tap DFE with adaptive CTLE and offset correction

  • Versatile x1 to x16 multi-protocol configurations

  • Support for PIPE 4.0 interface