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SerDes IP for SoC Designs | Cadence IP

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SerDes IP

Proven interoperability for versatile standards

Cadence® SerDes IP solutions address the performance, power, and area requirements of today’s mobile, consumer, and enterprise (infrastructure) markets with extensive standard support for the latest PCIe®, Ethernet, USB and MIPI® specifications.

Multi-protocol PHY is available for both low-power mobile applications and high-performance computing applications. The SerDes PHY IP is pre-integrated with Cadence controller and equipped with extensive test features for superior interoperability and the lowest risk path to System-on-Chip (SoC) success.

Benefits

  • Low power: low-active and low-leakage optimized design
  • High flexibility: flexible lane configuration with multi-protocol multi-link support
  • Low risk: extensive testability support for BIST, scan, loopbacks, SoC isolation, and on-chip eye plotter

News

"Cadence Unveils Broad IP Portfolio for New TSMC 16nm FinFET Plus Process"

"Simplifying Design and Verification of Advanced-Node Mobile SoCs Via Multi-Protocol PHY IP"

Products

16G Multi-Protocol PHYSilicon-proven IP that operates from 1.25Gbps to 16Gbps

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10G Multi-Protocol SerDesHighly optimized SerDes operating at speeds from 1.25Gbps to 10.40Gbps

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Protocol/Process Availability 

CATEGORY
PRODUCT
PROTOCOLS SUPPORTED
PROCESS
Ethernet 10G-KR IEEE 802.3 T28HPM, T28HPC,
MIPI D-PHY MIPI D-PHY v1.1 T16FF, T28HPM, T28HPC
 

M-PHY Gear 2

MIPI Specification for M-PHY v2.0 T28HPM,T28HPC, T28HPL, T40LP
PCIe PCIe 4.0 PCIe 1.0, 2.0, 3.0, and 4.0 T16FF+
  PCIe 3.0 PCIe 1.0, 2.0, and 3.0 T16FF, T28HPM, T28HPC
  PCIe 2.0 PCIe 1.0 and 2.0 T16FF, T28HPM, T28HPC
SerDes 16G Multi-Protocol

PCIe 4/3/2/1, USB 3.1 Gen 2 and Gen 1, 10G-KR, SATA3/2/1, SFP+, RXAUI, XAUI, QSGMII, SGMII

T16FF+
  10G Multi-Protocol SerDes

IEEE 802.3, and PCIe 3.0, 2.0 , 1.1 

T28HPM, T28HPC, T28HPC+