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SerDes IP

Proven interoperability for versatile standards

Cadence® SerDes IP solutions address the performance, power, and area requirements of today’s mobile, consumer, and enterprise (infrastructure) markets with extensive standard support for the latest PCIe®, Ethernet, USB and MIPI® specifications.

Multi-protocol PHY is available for both low-power mobile applications and high-performance computing applications. The SerDes PHY IP is pre-integrated with Cadence controller and equipped with extensive test features for superior interoperability and the lowest risk path to System-on-Chip (SoC) success.


  • Low power: low-active and low-leakage optimized design
  • High flexibility: flexible lane configuration with multi-protocol multi-link support
  • Low risk: extensive testability support for BIST, scan, loopbacks, SoC isolation, and on-chip eye plotter


112G Multi-Rate PAM-4 SerDesSilicon Proven, Long Reach, Low Power

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32/25G Multi-Protocol PHYSupporting multiple protocols with data rates up to 32Gbps

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16G Multi-Protocol PHYSilicon-proven IP that operates from 1.25Gbps to 16Gbps

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10G Multi-Protocol PHYHighly optimized SerDes operating at speeds from 1.25Gbps to 10.40Gbps

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UltraLink D2D PHYHigh-performance, low-latency PHY for die-to-die connectivity

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