PHY IP for PCI Express Enabling SoC Designs | Cadence IPPHY IP for PCI Express Enabling SoC Designs | Cadence IPPHY IP for PCI Express Enabling SoC Designs | Cadence IP

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PHY IP for PCI Express

The Cadence® PHY IP for PCIe is a state-of-the-art, high-end, silicon-proven SerDes offering PCIe end users the benefits they​ are looking for, regardless whether their application is consumer (mobile, IoT), enterprise (high-performance computing (HPC)/server/storage), artificial intelligence / machine learning (AI/ML), or automotive. These benefits include maximum throughput, ultra-low power operation, and minimum latency (normal mode and L1.1/1.2 sub-states exit latencies).​

PHY for PCIe 4.0 Block Diagram

Our SerDes family for PCIe offers optimized solutions for PCIe 5.0, 4.0, 3.1, 2.1, and 1.1. All of our SerDes IP exceed by far the​ specification in terms of equalization capability to offer peace of mind to our customers. We also provide a dedicated solution​ for long-reach applications where the loss is in excess of 30dB (30dB at 16Gbps, 35dB at 32Gbps). The Cadence PHY IP​ for PCIe supports different speeds simultaneously within the same macro (PCIe 5.0, 4.0, 3.1, 2.1, and 1.1). A multitude of test features are embedded and easily accessible by the end user to accelerate the bring-up phase. The last, but not least, feature is our user-friendly graphical interface that provides easy access to embedded BER and pattern testers and monitors to measure the link performance in real time.​

Benefits

  • High performance: Single macro supports max 32Gbps with up to 16 lanes for long-reach applications​
  • Mature and silicon proven: Compliance proven, customer SoCs in volume production​
  • Low risk: Fully validated by Cadence rigorous IP qualification process and system stress tests​
  • Ease of use: Fully verified pre-integrated IP delivery, with package and signal integrity support and firmware for rapid bring-up​