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PHY IP for PCI Express Enabling SoC Designs | Cadence IP

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PHY IP for PCI Express

The Cadence® PHY IP for PCIe® is a state of the art, high-end, silicon-proven SerDes offering the PCIe end-users the benefits they are looking for, regardless whether the application is consumer (mobile) or enterprise (server/storage). These benefits include maximum throughput, ultra low-power operation, and minimum latency (normal mode and L1.1/1.2 sub-states exit latencies).

PHY for PCIe 4.0 Block Diagram

Our SerDes family for PCIe offers optimized solutions for PCIe 4.0, 3.0, 2.0, and 1.0. All our SerDes IP exceeds by far the specification in terms of equalization capability to offer peace of mind to our customers. We also provide dedicated solution for Long Reach application where the loss is in excess of 30dB. Cadence PHY IP for PCIe supports different speeds simultaneously within the same macro (Gen4/3/2/1). A multitude of test features are embedded and easily accessible by the end-user to accelerate the bring-up phase. Finally the user-friendly graphical interface provides easy access to embedded BER and Pattern testers and monitors to measure the link performance in real time.

Benefits

  • Dedicated solutions optimized for consumer (mobile) and enterprise (server/storage)
  • Highly configurable and flexible for fastest system-on-chip (SoC) integration
  • Extra margins for error-free operation in demanding backplane application