Controller IP for PCI Express Enabling SoC Designs | Cadence IPController IP for PCI Express Enabling SoC Designs | Cadence IPController IP for PCI Express Enabling SoC Designs | Cadence IP

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Controller IP for PCI Express

The Cadence® Controller IP for PCIe® provides the logic required to integrate a Root Complex (RC), Endpoint (EP), or Dual Mode (DM) controller into any system on chip (SoC). Client applications access the controller through industry standard ARM® AMBA® 3 or 4 AXI interface or through the native HAL interface.

The Cadence Controller IP for PCIe is architected to quickly and easily integrate into any SoC, and to address a wide range of end customer applications, including storage solutions, server, and industrial applications.

Controller IP for PCIe Block Diagram

Cadence Controller IP for PCIe addresses a wide range of high-performance as well as low-power requirements for a broad spectrum of applications, including supercomputing platforms, storage solutions, server applications, and mobile platforms. The controller area is optimized for each application to provide you with the best power and performance.

Our controller IP for PCIe designs offer over 100 configurable features and 1,500 input parameters to optimize your design for the best area and performance for a specific application. Cadence controllers have been integrated with both Cadence and third-party PHY IP designs.

Cadence controller IP for PCIe designs are delivered as clear, readable, synthesizable RTL with STA scripts, comprehensive user guides, and documentation. The controller for PCIe product family also includes software drivers with reference integration code for Linux. You can accelerate software development on Cadence IP using our family of Virtual Reference Platforms.

Cadence has been a market leader in PCI-compliant controllers, and a significant number of X16 designs in silicon have been tested for interoperability and compatibility with a wide range of motherboards. Customers using our high-end designs have demonstrated performance that approaches the theoretical limits of throughput.

Cadence is an active member of the PCI-SIG and has presented at a number of DevCon events.



  • High performance—benchmarked at 95% of theoretical maximum throughput
  • Superscalar design for high performance, low latency, and high throughput

  • Configured to your specific needs – efficient implementation results in minimal gate count

  • Optimized for use with Cadence Multi-link PHY


Key Features

  • Compliant with PCIe 5.0, 4.0, 3.0, 2.1, and 1.1 specifications​

  • Single-root I/O virtualization (SR-IOV) and bifurcation options parity​

  • 500MHz or 1GHz core operation​

  • PIPE 5.x / PIPE 4.x compliant​

  • Configurable as root complex, endpoint, or dual mode devices​

  • MSI, MSIx, and legacy interrupts supported​

  • Ultra-low transmit/receive latency and high bandwidth​

  • Support for ECNs, ECR, ECRC, and end-to-end datapath parity​