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MIPI SoundWire Controller IP for SoC Designs | Cadence IP

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Controller IP for MIPI SoundWire

Today’s leading-edge mobile devices provide increasingly integrated functionality that enables growing volumes of content and video, more ways to control and interact, and longer battery life. The MIPI® Alliance defines semiconductor standards for mobile devices that support growing complexity and reduced device form factor.

The Cadence® IP Family for MIPI Protocols delivers area-optimized interface IP with the low power and high performance required for today's leading-edge devices. One member of this family is the Cadence Controller IP for MIPI SoundWire®, providing low-cost, low-power connectivity for audio data transport and control.

Developed by experienced teams with industry-leading domain expertise and extensively validated with multiple hardware platforms. The Controller IP is engineered to quickly and easily integrate with other MIPI compliant IP.

The Master and Slave Controller IP for MIPI SoundWire are part of the comprehensive Cadence Design IP portfolio comprised of Interface, memory, analog, and system and peripheral IP.

Products

Master Controller IP for MIPI Soundwire

The Cadence Master Controller IP for MIPI SoundWire v1.1 is a fully-verified, configurable, digital core that is compliant with the MIPI Alliance SoundWire specification.

It is an ideal solution for transporting audio and related data from baseband or application processors to audio devices.

Benefits

  • Full-featured and highly configurable IP core that is area-optimized for each application
  • Complete solution—complementary master/slave
  • Fully verified on FPGA

 

MIPI SoundWire Master Controller Block Diagram

The Master Controller IP for MIPI SoundWire v1.1 provides low-cost, low-power connectivity for audio data transport and control. SoundWire interface is utilized to provide two types of connectivity. The first carries PCM audio data between a mobile application processor and a standalone audio codec or Bluetooth®/FM radio controller. The second type carries PDM audio between the audio codec and MEMS microphone or speaker amplifiers.

The Controller IP uses a modular and layered design approach. Many configurable parameters are provided to customize client interface, FIFO width/depth, port count, lane count, clocking scheme, etc. for an area- and power-optimized solution.

The Controller IP comes with clean, readable, synthesize-able Verilog RTL, synthesis scripts, sample verificationtestbench with integrated BFM, monitors, and sanity tests and full set of documentation, including implementation specification, user guide and release history.

Features

  • MIPI compliant master controller with multi-lane capability
  • Configurable port, FIFO and interface features
  • Multi-entry command FIFO for READ/WRITE/PING commands

 

Slave Controller IP for MIPI Soundwire

The Cadence Slave Controller IP for MIPI SoundWire v1.1 is a fully-verified, configurable, digital core that is compliant with the MIPI Alliance SoundWire specification.

It is an ideal solution for transporting audio and related data from baseband or application processors to audio devices.

Benefits

  • Superior power and performance compared to other established audio connectivity standards
  • Complete solution - complementary master also available
  • Optimized for both SoC and Peripheral applications
MIPI SoundWire Slave Controller Block Diagram

The Slave Controller IP for MIPI SoundWire v1.1 provides low-cost, low-power connectivity for audio data transport and control. SoundWire interface is utilized to provide two types of connectivity. The first carries PCM audio data between a mobile application processor and a standalone audio codec or Bluetooth®/FM radio controller, while the second carries PDM audio between the audio codec and MEMS microphone or speaker amplifiers.

The Controller IP supports isochronous, TX-controlled, RX-controlled and fully asynchronous transport modes and standard-based frame parameters: offset and sub-frame offset, Hstart and Hstop, sample interval, BlockPackingMode, BlockGroupCount, LANESelect.

Many configurable parameters are provided to customize client interface, FIFO width/depth, port count, lane count, clocking scheme, etc. for an area- and power-optimized solution. 

The Controller IP comes with clean, readable, synthesize-able Verilog RTL, synthesis scripts, sample verificationtestbench with integrated BFM, monitors, and sanity tests and full set of documentation, including implementation specification, user guide and release history.

Features

  • MIPI compliant slave controller with multi-lane capability
  • APB Slave interface for control port and master configuration registers
  • APB Master interface for external user defined registers