MIPI SoundWire Controller IP for SoC Designs | Cadence IP

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MIPI SoundWire Controller IP

Today’s leading-edge mobile devices provide increasingly integrated functionality that enables growing volumes of content and video, more ways to control and interact, and longer battery life. The MIPI® Alliance defines semiconductor standards for mobile devices that support growing complexity and reduced device form factor.

The Cadence® IP Family for MIPI Protocols delivers area-optimized interface IP with the low power and high performance required for today's leading-edge devices. One member of this family is the Cadence IP for MIPI SoundWire Master Controller, providing low-cost, low-power connectivity for audio data transport and control.

Developed by experienced teams with industry-leading domain expertise and extensively validated with multiple hardware platforms. The Controller IP is engineered to quickly and easily integrate with other MIPI compliant IP.

The Cadence IP for MIPI SoundWire Master Controller is part of the comprehensive Cadence Design IP portfolio comprised of Interface, memory, analog, and system and peripheral IP.

Products

MIPI Soundwire Master Controller IP

The Cadence®  IP for MIPI® SoundWire Master Controller is a fully-verified, configurable, digital core that is compliant with the MIPI® Alliance SoundWire specification.

It is an ideal solution for transporting audio and related data from baseband or application processors to audio devices.

Benefits

  • Silicon-proven, in production by leading audio system-on-chip (SoC) providers
  • Verified with leading application processors

MIPI SoundWire Master Controller Block Diagram

The Cadence MIPI SoundWire Master Controller IP interface provides two representative types of connectivity. The first type carries PCM audio data between a mobile application processor and a standalone audio codec or Bluetooth/FM radio controller. The second type carries PDM audio data between the audio codec and MEMS microphone or speaker amplifiers.

Our IP uses a modular and layered design approach. The configurable parameters are provided to customize client interface, FIFO width/depth, port count, lane count, clocking scheme, etc. for an area- and power-optimized solution.

The IP comes with lint-clean, configurable, synthesizable Verilog RTL, synthesis and STA scripts, integration and user guide, release notes, and a sample verification testbench with integrated BFM and monitors.

Features

  • Standard-based master IP with multi-lane capability
  • AHB-based software control
  • Bi-directional or uni-directional FIFO-based physical data ports for low-latency audio streaming

 

 

MIPI Soundwire Slave Controller IP

The Cadence® IP for MIPI® SoundWire Slave Controller is a fully-verified, configurable, digital core that is compliant with the MIPI Alliance SoundWire specification.

It is an ideal solution for transporting audio and related data from baseband or application processors to audio devices.

Benefits

  • Silicon-proven, in production by leading audio system-on-chip (SoC) providers
  • Verified with leading application processors
MIPI SoundWire Slave Controller Block Diagram

The Cadence® IP Family for MIPI® protocols delivers area-optimized interface IP with the low power and high performance required for today's leading-edge devices. One member of this family is the Cadence IP for MIPI SoundWireSM Slave Controller, providing connectivity for audio data transport and control.

Developed by experienced teams with industry-leading domain expertise and extensively validated with multiple hardware platforms, the controller IP is engineered to quickly and easily integrate with other MIPI compliant IP.

The controller IP provides standard-based IP with multi-lane capability. It is designed to provide low-cost, low-power connectivity for audio data transport and control. The SoundWire interface is utilized to provide two types of connectivity. The first carries PCM audio data between a mobile application processor and a standalone audio codec or Bluetooth®/FM radio controller. The second type carries PDM audio between the audio codec and MEMS microphone or speaker amplifiers.

The slave controller supports isochronous, TX-controlled, RX-controlled and fully asynchronous transport modes and standard-based frame parameters: offset and sub-frame offset, Hstart and Hstop, sample interval, BlockPackingMode, BlockGroupCount, LANESelect.

The IP provides standard interface to the external PHY module with data, data enable, bus keeper enable signals, and slew rate control output.

Features

  • Standard-based slave IP with multi-lane capability
  • AHB-based software control
  • Bi-directional or uni-directional FIFO-based physical data ports for low-latency audio streaming