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MIPI I3C Controller IP for SoC Designs | Cadence IP

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MIPI I3C Controller IP

The rapidly increasing number of sensors creates new design challenges for mobile, automotive, and Internet of Things (IoT) devices. These challenges include significantly higher overall pin count and increased bandwidth requirements. To address these challenges the MIPI® Alliance has defined the I3C(SM) interface for connecting all sensors in the system with a single 2-wire high speed connection.

Compliant with the MIPI I3C and legacy compatible with I2C specification, the Cadence IP for MIPI I3C Master Controller is engineered to quickly and easily integrate into any mobile embedded system on chip (SoC) device and expand sensor communication capabilities with better performance and power efficiency.

Developed by an experienced team with industry-leading domain expertise and validated on a FPGA platform to reduce risk for designers, the IP will connect seamlessly to a Cadence IP for MIPI I3C Slave Controller.

The Cadence® IP Family for MIPI Protocols delivers area-optimized interface IP with the low power and high performance required for today's leading-edge devices.

The Cadence IP for MIPI I3C Master Controller is part of the comprehensive Cadence Design IP portfolio comprised of Interface, Memory, Analog, System and Peripheral IP.

Products

MIPI I3C Master Controller IP

The Cadence IP for MIPI I3C Master Controller is a digital core that is compliant with the latest MIPI I3C specification and legacy compatible with I2C. The Master Controller is engineered to quickly and easily integrate into any mobile SoC device and expand sensor communication capabilities with better performance and power efficiency.

Benefits

  • Superior performance to power ratio compared to established sensor interfaces - I2C, SPI

  • Complete solution—complementary master/slave IP

  • Fully verified on FPGA

Master Controller IP for MIPI I3C Block Diagram (click to enlarge)

The Master Controller is a soft IP ideally suited for implementation in ASIC SoC designs with increasing numbers and types of sensors. It provides reduced energy consumption and higher performance over legacy designs.

The Master Controller is split into hardware and software functions. The I3C manager handles packet forming and message handling in hardware. It includes an interconnect protocol and support for 32-bit APB slave mode to access the registers interface and external DMA. There is an optional FIFO to reduce load on the host servicing the I3C interface. It functions primarily as a master controller, with optional secondary master support.

The IP supports I3C standard-compliant protocols including legacy I2C mode, backward compatible to Fast Mode (FM—up to 400kHz) and Fast Mode Plus (FM+—up to1 MHz), single data rate I3C mode (up to 12.5 MHz), and optional High Data Rate (HDR-DDR). The IP features include I3C common command codes, dynamic address assignment, in-band interrupts, hot-join request, and mastership takeover request support.

Features

  • Support for multiple transmission modes: Single Data Rate (SDR) and High Data Rate (HDR)

  • Support for I3C common command codes

  • Dynamic address assignment (DAA) support

 

MIPI I3C Slave Controller IP

The Cadence Slave Controller IP for MIPI I3C is a digital core that is compliant with the latest MIPI I3C specification and legacy compatible with I2C. The Slave Controller is engineered to quickly and easily integrate into any mobile SoC device and expand sensor communication capabilities with better performance and power efficiency.

Benefits

  • Superior performance to power ratio compared to established sensor interfaces - I2C, SPI
  • Complete solution—complementary master/slave IP
  • Fully verified on FPGA
Slave Controller IP for MIPI I3C Block Diagram (click to enlarge)

The Slave Controller is a soft IP ideally suited for implementation in ASIC SoC designs with increasing numbers and types of sensors. It provides reduced energy consumption and higher performance over legacy designs.

The Slave Controller consists of three major modules: slave bus controller, common command codes (CCC) controller and frame generator. The slave device supporting HDR-DDR implements the APB interface and provides a simple payload control mechanism FIFO for the read and write data.

The HDR-DDR data payload FIFO will be accessible using the APB register interface so the firmware can perform a single read address access to the FIFO for each packet of data and cyclic redundancy check (CRC) received, and a single address write to the FIFO for data, payload and CRC for any master HDR-DDR read transaction.

Features

  • Support for multiple transmission modes: Single Data Rate (SDR) and High Data Rate (HDR)

  • Dynamic address assignment (DAA) support

  • Support for in-band interrupts, hot-join, mastership request