MIPI CSI-2 Transmitter for SoC Designs | Cadence IP

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MIPI CSI-2 Transmitter

The Cadence® Transmitter (TX) Controller IP for MIPI® Camera Serial Interface 2 (CSI-2SM) is responsible for handling image sensor data in multiple RGB, YUV, and RAW formats, as well as user-defined data formats, and converting these into CSI-2-compliant packets for transmission over a D-PHYSM interface via the PPI interface. 

Benefits

  • Complete solution-complementary master/slave IP

  • Multi-stream pixel interface support

  • Automotive variant with safety manual

MIPI CSI-2 Transmitter Controller Block Diagram

The TX Controller IP for CSI-2 can handle up to four independent pixel streams and can perform Virtual Channel and Data Type interleaving before transmission on up to four PPI data lanes.

Developed by experienced teams with industry-leading domain expertise and extensively validated with multiple hardware platforms, the TX Controller IP for CSI-2 is engineered to quickly and easily integrate into any system- on-chip (SoC) design, and to connect seamlessly to a Cadence or third-party PPI-compliant D-PHY lane modules. The TX Controller IP for CSI-2 is part of the comprehensive Cadence Design IP portfolio comprised of interface, memory, analog, and system and peripheral IP.

Features

  • Compliant with MIPI CSI-2 v2.1 Specification

  • Support for MIPI D-PHY v2.1 specification, with 8-bit PPI data width and links with 1, 2, or 4 data lanes
  • Provides up to 4 independent stream input interfaces, with a highly configurable range of options, including multiple pixel modes, various buffering modes, packed data mode, and Data Type interleaving
  • Optional extensions for loopback support on stream 0,for connection to Cadence Receiver Controller IP forCSI-2 (“RX Compatibility” mode)
  • Programmable Data Type and Word Count settings, with either 8 or 16 options selectable on a packet-by- packet basis
  • 32-bit Arm® AMBA® Slave programming interface

  • LRTE – Efficient Packet Delimiter support (Option 1 and 2)

  • Support for external RAM/register or internal register-based stream buffer
  • Support for all primary and secondary data formats
  • Supports ULPS on all data lanes and clock lane