MIPI CSI-2 Transmitter for SoC Designs | Cadence IP

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MIPI CSI-2 Transmitter

The Cadence Transmitter Controller IP for MIPI Camera Serial Interface 2 (CSI-2SM) s a fully-verified configurable digital core that is compliant with the MIPI Alliance CSI-2 v1.3 specification. The Controller IP handles MIPI CSI‑2 protocol, providing serial pixel outputs for interfacing to an image signal processor (ISP).

It is an ideal solution to provide a high-speed serial interface between an application or image processor and MIPI CSI-2 compliant camera sensor.


  • Full Featured and highly configurable IP core that is area-optimized for each application
  • Complete solution–complementary master/slave IP
  • Fully verified on an FPGA

The Controller IP, compliant with the MIPI® Alliance CSI-2 v1.3 specification, provides a high-speed serial interface between an application processor and a MIPI CSI-2-compliant camera sensor. The Controller IP interface connects with the physical layer (MIPI D-PHY) through the MIPI-recommended PHY Protocol Interface (PPI). The design supports all preliminary and secondary video formats.

As a camera serial interface that processes each control or pixel data packet (such as RAW, RGB, YUV), the Controller IP reorders up to four 2.5Gbps data lanes, distributes the high-speed byte clock of D-PHY to the CSI2-TX D-PHY interface active byte lanes, and divides a pixel packet or 32-bit words into bytes for the active data lanes.

The Controller IP offers a variety of features, including dynamic lane distribution, support for all primary and secondary data formats, 32-bit APB slave interface for register access ,as well as virtual channel management and data type interleaving.

MIPI CSI-2 Transmitter Controller Block Diagram

Cadence provides you with a complete, single-vendor MIPI CSI-2 solution together with our proven Cadence MIPI D-PHY IP to help improve your time-to-market while reducing integration risk and cost. The Controller IP provides a cost-effective, low-power camera-interface solution for application processors and media processors used on the mobile market.


  • Each data lane supports up to 2.5Gbps (MIPI D-PHY v1.2)
  • Up to four pixel stream inputs
  • Virtual channel management and data interleaving