MIPI CSI-2 Transmitter for SoC Designs | Cadence IP

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MIPI CSI-2 Transmitter

The Cadence® MIPI® CSI‑2 Transmitter IP s a fully-verified configurable digital core that is compliant with the MIPI Alliance CSI-2 specification. The IP handles MIPI CSI‑2 and SMIA CCP2 protocols, providing both serial pixel outputs for interfacing to an image signal processor (ISP) and packed data outputs for direct-to-memory applications.

It is an ideal solution to provide a high-speed serial interface between an application or image processor and MIPI CSI-2 compliant camera sensor.  


  • Pre-integrated and verified DSI solution with Cadence MIPI D-PHY IP
  • Rich system bus for easy integration
  • Support for variable refresh rates

The Cadence MIPI CSI-2 Transmitter Controller IP, compliant with the MIPI® Alliance CSI-2 specification, provides a high-speed serial interface between an application processor and a MIPI CSI-2-compliant camera sensor. MIPI CSI-2 TX Controller IP interfaces with the physical layer (MIPI D-PHY) through the MIPI-recommended PHY Protocol Interface (PPI). The design supports all preliminary and secondary video formats.

As a camera serial interface that processes each control or pixel data packet (such as RAW, RGB, YUV), the Cadence MIPI CSI-2 Transmitter IP reorders up to four 1.5Gbps data lanes, distributes the high-speed byte clock of D-PHY to the CSI2-TX D-PHY interface active byte lanes, and divides a pixel packet or 32-bit words into bytes for the active data lanes.

The Cadence MIPI CSI-2 Transmitter IP offers a variety of features, including ECC and CRC error detection, configurable asynchronous FIFO for each pixel stream, gate clocking for low-power operation, as well as virtual channel management and data interleaving.

MIPI CSI-2 Transmitter Controller Block Diagram

Cadence provides you with a complete, single-vendor MIPI CSI-2 solution together with our proven Cadence MIPI D-PHY IP to help you improve your time-to-market while reducing integration risk and cost. The Cadence MIPI CSI-2 Transmitter IP provides a cost-effective, low-power camera-interface solution for application processors and media processors used on the mobile market.


  • Bandwidth: from one to four lanes for each virtual channel
  • Local Bus interface: APB for configuration
  • Virtual channel management and data interleaving