MIPI M-PHY IP for SoC Designs | Cadence IP

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MIPI M-PHY IP

The Cadence® Design IP for MIPI® M-PHY® is a mixed-signal PHY IP that integrates a MIPI M-PHY transmitter (M-TX) , MIPI M-PHY receiver (M-RX), and a low-speed transceiver that supports both SYS and PWM modes.

The M-PHY IP is designed to employ modular implementation with scalability for up to four lanes in one sub-link, offering great SoC flexibility.

The M-PHY IP is a cost-effective, low-power solution for demanding mobile applications. The modular implementation approach gives you the greatest flexibility to connect up to four lanes per SUB-LINK in parallel for increased throughput. Integrated functionality is the driver for today’s leading-edge mobile devices that contain solutions enabling growing volumes of content and video, more ways to control and interact, and longer battery life usage.

Benefits

  • Proven design in volume production
  • Scalable LANE module offer great SoC flexibility
  • Extensive testability enable low risk development and fast TTM

MIPI M-PHY Block Diagram

Using the Cadence Design IP for M-PHY with Cadence Controller IP for MIPI, customer receives a complete, single-vendor solution for MIPI M-PHY applications.

The M-PHY IP is architected to quickly and easily integrate into any design and to connect seamlessly to a Cadence, or third-party, RMMI-compliant controller. It has passed silicon validation in different process nodes and provides a cost-effective, low-power interface solution for application processors and media processors used on the mobile market.

Features

  • Mobile-optimized area and power
  • Configurable as Type-I or Type-II MODULE
  • Integrated built-in self test (BIST) capable of producing and checking PRBS, CRPAT, and CJTPAT