MIPI DSI Transmitter for SoC Designs | Cadence IP

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MIPI DSI Transmitter

The Cadence® MIPI® DSI Transmitter IP is fully configurable and compliant with the MIPI Alliance DSI specification. The Cadence MIPI DSI Transmitter IP interfaces with the physical layer (MIPI D-PHY) through the MIPI-recommended PHY Protocol Interface (PPI).

It provides a high-speed serial interface between an application processor and MIPI DSI-compliant display. The Cadence MIPI DSI Transmitter IP is ideal for use in video and command display applications.  

Benefits

  • Pre-integrated and verified DSI solution with Cadence D-PHY
  • Rich system bus for easy integration
  • Support for variable refresh rates

MIPI DSI Transmitter Block Diagram

The Cadence MIPI DSI Transmitter IP, compliant with the MIPI® Alliance DSI specification, provides a high-speed serial interface between an application processor and a MIPI DSI-compliant display module. The MIPI DSI Transmitter IP interfaces with the physical layer (MIPI D-PHY) through the MIPI-recommended PHY Protocol Interface (PPI). Using up to four 1.5Gbps D-PHY data lanes, the design ensures full support for DPI and DBI, while also offering low-power operation through various power consumption modes.

The Cadence MIPI DSI Transmitter IP is feature-rich, with Tearing Effect (TE) for command display, bus contention recovery support, gate clocking, and ULPS for power-optimized operation, a very wide display format support, and dynamic switching of the DSI link between the video and command mode without resetting the IP.

We provide you with a complete, single-vendor MIPI DSI solution together with the proven Cadence MIPI D-PHY IP to help you improve time-to-market while reducing integration risk and cost. The Cadence MIPI DSI Transmitter IP provides a cost-effective, low-power display interface solution for application processors and media processors used on the mobile market.

Features

  • Bandwidth: from one to four lanes supported
  • Dynamic switching: video and command mode
  • Local bus interface: APB, DPI, and DBI