MIPI D-PHY IP for SoC Designs | Cadence IPMIPI D-PHY IP for SoC Designs | Cadence IPMIPI D-PHY IP for SoC Designs | Cadence IP

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The Cadence® MIPI® D-PHY integrates a high-speed transmitter/receiver, low-power transmitter/receiver, and low-power contention detector that provide the full function of D-PHY. Our IP is based on the latest MIPI D-PHY specification and has an integrated PPI interface for ease-of-integration with MIPI CSI-2 and DSI controllers.

Given its modular implementation, the Cadence MIPI D-PHY provides great lane flexibility with compact and rectangular IP footprint, meeting diversified usage models of modern system-on-chip (SoC) design needs. The pre-integrated CSI-2 and DSI solution ensures the interoperability and makes this PHY easy to integrate, shortening the product time-to-market.


  • Pre-integrated CSI-2 and DSI solution
  • Scalable modular design with compact and rectangular footprint
  • PHY hardware evaluation platform
MIPI D-PHY Block Diagram

With our Cadence MIPI D-PHY IP, we provide you with a complete, single-vendor MIPI CSI-2 and DSI solution together with our proven MIPI CSI-2 controller and DSI controller to help you improve your time-to-market while reducing integration risk and cost.

You get a cost-effective, low-power MIPI D-PHY solution for application processors and media processors used on the mobile market. Our architecture supports connection of multiple data lanes in parallel, the aggregated throughput of a common four data lane configuration is 6Gbps and 10Gbps for specification v1.1 and v1.2, respectively.


  • TX-only (with integrated PLL), RX-only, and combined TX and RX configurations
  • Complete function for HS TX/RX, LP TX/RX, and LPCD with automatic termination control for high-speed and low-power modes
  • Integrated BIST capable of producing and checking PRBS, CRPAT, and CJTPAT