MIPI CSI-2 Receiver for SoC Designs | Cadence IP

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MIPI CSI-2 Receiver

The Cadence® Receiver (RX) IP for MIPI® CSI-2SM is a fully-verified, configurable, digital core that is compliant with the MIPI Alliance CSI-2 v2.1 specification. The Controller IP is responsible for handling and decoding CSI-2 protocol-based camera or other sensor data stream and managing the forwarding or unpacking of payload data to the pixel-stream interfaces. It is an ideal solution to provide a high-speed serial interface between an application or image processor and MIPI CSI-2 compliant camera sensor.

Benefits

  • Full featured and highly configurable IP core that is area optimized for each application

  • Complete solution with complementary master/slave IP

  • Fully verified on an FPGA

  • Automotive variant with Safety Manual

MIPI CSI-2 Receiver Block Diagram

The RX Controller IP for CSI-2 allows the selection of multiple independent streams to support the control of the destination for each data packet (for example, Bayer input of ISP, RGB/YUV input of ISP, or DMA to memory).

The RX Controller IP for CSI-2 consists of a lane management module that connects via the PHY-Protocol Interface (PPI) to a D-PHY receiver module, an external register interface for configuration of the receiver IP, a CSI-2 protocol module for protocol decode, and a CSI-2 stream module for providing received CSI-2 packets from the D-PHY and providing synchronization information and pixels/packed data to the pixel stream interface. Each stream has an external memory interface that can act as a line buffer or as a short buffer to minimize latency.

Features

  • Compliant with MIPI CSI-2 v2.1 Specification
  • Support for MIPI D-PHY v2.1 specification, with 8-bit and 16-bit PPI data width and links with 1, 2, 4, or 8 data lanes
  • Provides up to 8 independent stream output interfaces, with a highly configurable range of options, including multiple pixel modes, various buffering modes, packed data mode, Data Type selection, and Virtual Channel or Data Type interleaving
  • Protocol-only support (no stream modules) for raw decode of CSI packets and error detection, providingextremely low gate count
  • Configurable internal data path width of 32 or 64 bits to allow system clock frequency reduction
  • 32-bit Arm® AMBA® APB Slave programming interface
  • LRTE – Efficient Packet Delimiter support (Option 1 and 2)
  • Support for external RAM/register or internal register-based stream buffer
  • Support for all primary and secondary data formats
  • Supports ULPS on all data lanes and clock lane