Ethernet SerDes for SoC Designs | Cadence IPEthernet SerDes for SoC Designs | Cadence IPEthernet SerDes for SoC Designs | Cadence IP

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Ethernet SerDes

The Cadence® Ethernet SerDes IP family features intellectual property blocks that you can easily and quickly integrate into your design. The family includes 10G-KR PHY IP and 10G-KR Multi-Protocol PHY IP. Ideal for use in Ethernet connectivity applications that require fixed-wire communication,such as home gateways, set-top boxes, TVs, printers, projectors, and other devices.


  • Cost effective solution versus off-chip PHY
  • Low risk with pre-verified characterized and certified IP
  • Complete subsystem with co-integration of MAC and PHY

Cadence 10G-KR PHY Block Diagram

The Cadence Ethernet SerDes IP is a product family that includes the following IP blocks which can beeasily and quickly integrated into your design:

  • 10G-KR PHY IP
  • 10G-KR Multi-Protocol PHY IP

The Cadence 10G-KR PHY IP targets performance-driven applications such as 10G/40G and 100GEthernet, PCIe® backplanes, as well as XAUI enterprise and network devices.

Compliant with IEEE 802.3 10GBase-KR requirements, PCI Express® 3.0, 2.0, and 1.1, and XAUI, the Cadence 10G-KR Multi-Protocol PHY IP is highly configurable, so that you can utilize a single PHY for multiple applications.