DisplayPort TX PHY for SoC Designs | Cadence IP

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DisplayPort TX PHY

Benefits

  • Optimum SoC configurability
  • Optimized PPA for mobile and consumer applications
  • Extensive BIST and DFT enable ease of integration, faster bring-up, and quick debugging

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The Cadence® DisplayPort/embedded DisplayPort TX IP provides a configurable PHY IP that simplifies the design process without compromising performance, power or silicon die area. The PHY IP is a lower-active and low leakage power design crafted for mobile, wireless IoT, and consumer designs.

IP for DisplayPort/Embedded DisplayPort TX PHY Block Diagram

The PHY IP is a derivative design from a successful and proven Cadence 10Gbps multi-protocol multi-link PHY, carrying all the good attbritures from original architecture (low power, flexible configurability, eas-of- use) with further optimization on reducing the IP area. The PHY IP provides a raw SerDes interface for controller interface.

Features

  • DisplayPort and embedded Display/Port v1.4
  • Support RBR, HBR, HBR2, HBR3
  • Support wide range of reference clock rates
  • Support both internal and external clock sources
  • Automatic calibration of on-chip termination resistors
  • Flexible lane configuration from 1 to 8 lane
  • Optional AUX channel support
  • SCAN, BIST, and serial/parallel loopback functions

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