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PHY IP for CCIX Enabling SoC Designs | Cadence IP

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PHY IP for CCIX

The Cadence® 25Gbps Multi-Link and Multi-Protocol PHY IP for TSMC 7nm is a high-performance SerDes operating from 1.25 to 25Gbps specifically designed for infrastructure and datacenter applications. It features long reach equalization capability at very low active and standby power. The SerDes offers very low latency for time critical application for enterprise-level data communications, networking, and storage systems.

PHY IP Interfaces

The PHY IP provides extensive flexibility to mix and match protocols within the same macro. The PHY IP is designed to simultaneously run PCIe®, CCIX, USB, SATA, 10G-KR, XAUI/RXAUI, and SGMII on a per lane basis. Multiple test features are embedded and easily accessible by the end-user. A user-friendly graphical interface called EyeSurfTM provides convenient access to real-time and non-destructive eye scope and bathtubs for monitoring the bit error rate (BER) and the link performance during live traffic.

Benefits 

  • Maturity – Silicon proven and robust Serdes architecture
  • Flexibility – Maximum flexibility and reconfigurability
  • Ease-of-use – Faster to integrate, bring-up, and support

Key Features

  • High performance PHY for datacenter applications
  • Low-latency, long reach and low power modes
  • Wide range of protocols that support networking, storage and computing applications
  • Multi-Link PHY—mix protocols within the same macro
  • EyeSurf —non-destructive on-chip oscilloscope
  • Extensive set of isolation, test modes and loop-backs including APB and JTAG
  • Supports 16-bit, 20-bit, and 32-bit PIPE and non-PIPE interfaces
  • Selectable serial pin polarity reversal for both transmit and receive paths