PHY IP for CCIX Enabling SoC Designs | Cadence IPPHY IP for CCIX Enabling SoC Designs | Cadence IPPHY IP for CCIX Enabling SoC Designs | Cadence IP

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The Cadence® 32/25Gbps Multi-Protocol PHY IP for TSMC 7nm is a high-performance SerDes operating from 1.25Gbps to 32Gbps and specifically designed for infrastructure and datacenter applications. It features long-reach equalization capability at very low active and standby power. The SerDes offers very low latency for time-critical applications for enterprise-level data communications, networking, and storage systems.​

PHY IP Interfaces

The PHY IP provides extensive flexibility to run PCIe®, CXL 25G-KR, 10G-KR, and SGMII/QSGMII.​ Multiple test features are embedded and easily accessible by the end-user. A user-friendly graphical interface called EyeSurf provides convenient access to real-time and non-destructive eye scope and bathtubs for monitoring the bit error rate (BER) and the link performance during live traffic.​


  • Maturity – Silicon proven and robust Serdes architecture
  • Flexibility – Maximum flexibility and reconfigurability
  • Ease-of-use – Faster to integrate, bring-up, and support

Key Features

  • High performance PHY for datacenter applications
  • Low-latency, long reach and low power modes
  • Wide range of protocols that support networking, storage and computing applications
  • EyeSurf —non-destructive on-chip oscilloscope
  • Extensive set of isolation, test modes and loop-backs including APB and JTAG
  • Supports 16-bit, 20-bit, and 32-bit PIPE and non-PIPE interfaces
  • Selectable serial pin polarity reversal for both transmit and receive paths