Controller IP for CCIX Enabling SoC Designs | Cadence IPController IP for CCIX Enabling SoC Designs | Cadence IPController IP for CCIX Enabling SoC Designs | Cadence IP

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Controller IP for Cache Coherent Interconnect for Accelerators (CCIX)

The Cadence® Controller IP for CCIX is built on top of our mature PCI Express solution that is widely deployed in multiple products in production. It provides shared data access significantly improving compute efficiency for servers running data center workloads. The Controller IP is engineered to quickly and easily integrate into any system-on-chip (SoC) and connect seamlessly to a Cadence or 3rd-party PIPE 4.x-compliant PHY.

Controller IP Interfaces

The Controller IP is part of the comprehensive Cadence Design IP portfolio comprised of interface, Denali memory interface, analog, and systems and peripherals IP.


  • Faster system integration with pre-integrated PHY, controller, drivers, and verification IP
  • Reduced risk from using silicon-proven PCI Express 4.0 solution
  • Higher quality from applying complete Cadence verification solution

Key Features

  • Optimized, tightly coupled interface between processors and accelerators
  • Low-latency interface
  • Built on robust PCI Express 4.0 solution (can run in PCIe-only mode) with CCIX specific transaction layer
  • Dedicated AXITM4 interface for priority traffic (QoS)
  • Support for Vendor Defined Messages (VDMs) and optimized Transition Layer Packets (TLPs)