Fusion DSPs for IoT and General Purpose DSP

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Tensilica Fusion DSP Family

Multi-Purpose DSPs for Any Application

Fusion DSP dataplane diagram

No standard processor can meet the varied demands of any type of application, until now. The Cadence Tensilica Fusion family is a scalable range of general purpose DSP processors designed with flexible options to give designers the ability to shape the DSP into exactly what their application needs. 

From ultra-low power, small footprint to compute-intensive, high performance processing, the Tensilica Fusion DSPs are ideal for any SoC application including IoT, Automotive, Mobile, Wearables, Consumer, and much more. 

Based on the 32-bit Xtensa® control processor with market-leading DSP features, including algorithm-specific operations for a fully programmable approach, designers get all of the customization advantages that Tensilica processors are known for, along with incredible flexibility. Tensilica Fusion DSPs can support multiple existing and developing standards, as well as customer specific algorithms.

Designers can use the Xtensa Xplorer GUI for choosing options and configurations, to create an optimal and energy-efficient Fusion DSP specifically suited to their application. With optimized pre-verified options, designers can build thier processor and get up and running quickly, with minimal verification effort, significantly reducing time-to-market.

Fusion DSP Family

Tensilica Fusion F1 DSP

A Proven Base Architecture with Lots of Flexibility

The Tensilica Fusion F1 DSP offers low energy, high performance control and signal processing for a broad segment of IoT/wearable markets. This highly configurable architecture is specifically designed to excel at always-on processing - including wake-on-voice and sensor fusion applications - that require a merged controller plus DSP, ultra-low energy, and a small footprint. It can be designed into SoCs for wearable activity monitoring, indoor navigation, context-aware sensor fusion, face trigger, voice trigger, and voice recognition.

Additionally, the Tensilica Fusion F1 DSP is very efficient in running the narrowband wireless communications standards typically associated with IoT device communications, including protocols such as Bluetooth Low Energy, Thread and Zigbee using IEEE 802.15.4, SmartGrid 802.15.4g, Wi-Fi 802.11n and 802.11ah, 2G and LTE Category 0 release 12 and 13, and global navigation satellite systems (GNSS).

Feature Supported Benefits
VLIW Slots 2 Allows two concurrent operations
Fixed-point MACs per Cycle One 32x32
Two 24x24
Two 16x16 (four optional)
Flexible MAC architecture efficiently handles broad set of data types
Accumulator 64-bit
ITU/ETSI Intrinsics Yes Accelerates ITU/ETSI voice codec performance
Circular Buffer Yes Efficiently manage streams of data
Customer-defined Instructions for Further Optimization Yes Extend the ISA to efficiently meet customer requirements
Prefetch for Cache-based Configurations Optional Improves cache memory performance

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Tensilica Fusion G3 DSP

Exceptional Out-of-the-Box DSP Performance for all Applications

The Fusion G3 DSP is an easy to program, fixed and floating point DSP, with rich instruction set architecture (ISA), ideal for multi-purpose applications in automotive, consumer, IoT and industrial markets. 

The Tensilica Fusion G3 DSP is built on the proven Xtensa real-time control processor and has a flexible memory subsystem, optional integrated DMA controller and memory protection unit (MPU), making it an excellent choice for standalone DSP SoC designs.

The Fusion G3 features a 128-bit, 4-slot VLIW architecture with a high performance 11-stage DSP pipeline. The Fusion G3 boasts high DSP performance with quad 32-bit integer MACs and quad single precision 32-bit floating point Fused Multiply Adds (FMAs) or MACs, ideal for compute-intensive applications including mid- to high-end audio pre and post processing, radar, low end image processing.

The Fusion G3 combines high performance signal processing, with unrivalled configurability and extensibility, giving customers the ultimate in flexibility of hardware and software design choices to meet their application needs.

And with industry-leading advanced development tools, including auto-vectorizing compiler, and extensive DSP software library support, the Tensilica Fusion G3 DSP provides designers with an easy development flow with exceptional performance right out-of-the-box for their next generation applications.   

Tensilica Fusion G3 Feature Overview

Feature Supported Benefits
128-bit 4-slot VLIW DSP Architecture 4-slots High performance and more DSP operation parallelism
128-bit SIMD Architecture 4-way (32-bit) Multi-way data depending on the data type size
Rich DSP instruction set architecture (ISA) check mark Suitable for many DSP applications
Fixed-point (32-bit) MACs per Cycle 4 4x32-bit, 8x16-bit and 16x8-bit MACs/cycle
Floating point single precision (32-bit) FMAs or MACs per Cycle 4 Up to 16GLFLOPS@1GHz
Optional memory protection unit (MPU) check mark Configurable sizes and protection schemes
Optional integrated direct memory access (DMA) controller check mark Improve data movement efficiency and hide latencies
Xtensa LX7 based 32-bit control processor check mark Excellent real-time control and compatibility with all Tensilica processors
Auto vectorizing compiler plus software DSP library check mark Easy C programming, high performance 'out-of-the-box' with easy porting of code
Scatter/gather/histogram supported operations check mark Capable of low-end image processing and pattern recognition
Optional ECC/Parity check mark On instruction and data caches, L1 memories on the system bus interface

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Design Tools

Port C to FFT

Port Software Quickly in C

A key advantage of the Fusion DSPs are that they use a simple programming model. Software developers can port audio, voice, and enhancement software codecs completely in C, while maintaining or surpassing the performance of assembly on other DSP and CPU architectures. This minimizes the time required to port and maintain special or proprietary software. 

Processor design process

For Processor Designers

We deliver patented, proven tools that automate the process of generating your Tensilica Fusion DSP, along with matching software tools. These tools have been proven in thousands of designs and the results are guaranteed correct by construction.

View the complete set of tools for processor designers.

Softwre development process

For Software Developers

For Software DevelopersThe Xtensa Software Developer's Toolkit provides a comprehensive collection of code generation and analysis tools that speed the software development process. The Cadence Tensilica Eclipse-based Xtensa Xplorer Integrated Development Environment (IDE) serves as the cockpit for the entire development experience.

View the complete set of tools for software developers.

BDTI Evaluation Report

The Tensilica Fusion G3 DSP is "signficantly more cycle efficient on every benchmark" and "34% faster" against an industry standard DSP. Read more about the Fusion G3 DSP in the BDTI Evaluation Report

Introductory Videos


Fusion F1 DSP
Fusion G3 DSP

White Papers

Fixed- and Floating-Point FMCW Radar Signal Processing with Tensilica DSPs
Keeping Always-On Systems On for Low-Energy Internet-of-Things Applications
Managing Multiple Wireless Standards for Smart Home Applications
Meeting Multiple IoT Application Requirements with a Single, Configurable DSP Core

Press Releases

Cadence Launches Tensilica Fusion G3 DSP Featuring Exceptional Out-of-the-Box Performance for Compute-Intensive Signal Processing Applications

New Tensilica Fusion DSP Sets Low-Energy Benchmarks for IoT, Wearables and Wireless Connectivity

More Videos

Chris Rowen talks about techniques for optimizing power in sensor-based IoT devices and always-on subsystems

Chris Rowen takes a look at how a configurable processor provides the flexibility to optimize power for a given application

Paul Garden talks about the Fusion G3's 128-bit SIMD ALU, instruction formats, auto-vectorizing compiler and software DSP library