DDR IP for SoC Designs | Cadence IPDDR IP for SoC Designs | Cadence IPDDR IP for SoC Designs | Cadence IP


Cadence® Denali® DDR Memory IP is a family of system-level IP solutions consisting of memory controller and memory PHY IP. Our DDR IP offering addresses a broad range of high-performance and low-power requirements for today’s ever-changing environment.

We offer DDR controller and PHY IP that supports all widely used DDR protocols, including GDDR6, HBM2E, HBM2, LPDDR5, LPDDR4X, LPDDR4, LPDDR3, DDR5, DDR4, DDR3, and DDR3L. The DDR Controller IP is extremely flexible and can be configured to support almost any application. Two DDR PHY architectures, high-speed (HS) PHY and low-power (LP) PHY, are designed to provide you with configurable solutions that meet the specific needs of your system and application.

Controller and PHY for DDR5

Cadence has prototyped the world’s first IP interface in silicon for a DDR5 standard developed by JEDEC. The test chip contains the next-generation memory interface IP based on the industry consensus of the DDR5 standard, and Micron has supplied prototype DRAM chips. The test chip was fabricated in a 7nm process and contains both the controller and PHY. The prototype successfully achieves 4400 megatransfers per second, 37.5% faster than the fastest commercially available DDR4 memory. 

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