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112G Multi-Rate PAM-4 SerDes


  • Unique firmware-controlled adaptive power design provides optimal power and performance tradeoffs and more efficient system designs based on platform requirements

  • DSP-based architecture provides superior data recovery for lossy and noisy channels

  • Extended reach capability enables customers to use lower cost PCBs and achieve greater flexibility in PCB and system design

  • Multi-rate support, including 112/56Gbps PAM-4 as well as 56/28/10Gbps NRZ for backward compatibility with legacy equipment operating at lower speeds

  • Fully autonomous startup and adaptation, as well as integrated BIST capable of producing and checking PRBS are supported to enhance IP ease of use

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The Cadence® 112Gbps Multi-Rate PAM-4 SerDes IP in 7nm semiconductor process technology delivers industry-leading power, performance and area (PPA) ideal for building high-port density networking products for next-generation cloud-scale and telco datacenters.

112G Multi-Rate PAM-4 SerDes Test Chip and Demonstration Board

Market Requirements

Escalating mobile data consumption, burgeoning AI and machine learning applications, and emerging 5G communications requirements that demand ever-increasing bandwidth are straining the existing cloud datacenter server, storage and networking infrastructure.

Early adopters in the high-end cloud datacenter market are now installing 400G Ethernet ports, with 400G Ethernet expected to go mainstream in 2020 as early adopters begin 800G Ethernet deployment.

Long-Reach Challenges

112G SerDes technology doubles the data rate of 56G SerDes, meeting the exploding high-speed connectivity needs for emerging data-intensive applications such as machine learning and neural networks. However, the long-reach connections needed in advanced server and networking equipment are notoriously difficult to design. Channel loss for long-reach applications at the 112G Nyquist frequency is much greater than medium-reach applications, demanding novel approaches to SerDes design.

Cadence Solution

The Cadence® 112Gbps Multi-Rate PAM-4 SerDes IP meets the challenge with:

  • ADC/DSP-based precise receive channel equalization

  • DAC-based transmitter with FIR filter

  • Continuous SNR monitoring and adaptation

  • Firmware-based adaptive power optimization

The multi-rate SerDes IP supports true plesiochronous operation at the data rates shown within +/- 200ppm. An integrated microcontroller allows for fully autonomous startup, adaptation, and service operation without requiring ASIC intervention. A programming and observation interface is provided via a parallel bus with MDIO-style addressing (port, device, address).

There are several comprehensive on-chip diagnostic tools that enable testability and easy debugging. A post-equalized histogram is available for accurate estimation of bit error rate (BER) even in the absence of actual bit errors. Vertical eye statistics can be logged to allow optional optimization of the device settings. The channel estimation hardware allows the accurate measurement of the channel response to assess package, connector, and trace characteristics. Integrated BIST is capable of producing and checking pseudorandom binary sequences (PRBS).

Supported data rates and modulation methods are shown below.

Encoding Data Rate
PAM-4 full-rate 103.125Gbps, 106.25Gbps
PAM-4 half-rate 51.5625Gbps, 53.125Gbps
NRZ full-rate 51.5625Gbps, 53.125Gbps
NRZ half-rate 25.78125Gbps, 26.5625 Gbps
NRZ 10G 10.3125Gbps
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