10G Multi-Protocol SerDes for SoC Designs | Cadence IP10G Multi-Protocol SerDes for SoC Designs | Cadence IP10G Multi-Protocol SerDes for SoC Designs | Cadence IP

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10G Multi-Protocol PHY

The Cadence® IP for 10Gbps Multi-Protocol PHY provides a flexible PHY IP that simplifies the design process without compromising performance, power, or silicon die area. The PHY IP is a lower active and low leakage power design crafted for mobile, wireless IoT, consumer, and automotive designs. The PHY IP is designed for multi-protocols running on a single PHY macro and is compliant with USB 3.1, PCI Express® (PCIe® ) 3.1, DisplayPort TX v1.4, Embedded DisplayPort TX v1.4b, SATA 3, QSGMII, and SGMII specifications. The PCS complies with the PIPE 4.x interfaces, and provides support for the dynamic equalization features of different protocols.​


Multi-Protocol SerDes (=PMA) Block Diagram - Overview


  • Multi-protocol multi-link offers optimum SoC configurability​

  • Optimized PPA for mobile and consumer applications​

  • Extensive BIST and DFT enable ease of integration, faster bring-up, and quick debugging​

Key Features

  • Supports USB 3.1, PCIe 3.0/2.0/1.0, DP-TX v1.4/eDP-TX v1.4b, SATA 3, and SGMII​

  • Multi-protocol support for simultaneous independent links

  • Supports SRIS and internal SSC generation

  • Supports PCIe L1 sub-states

  • Automatic calibration of on-chip termination resistors​

  • Supports internal and external clock sources with clock active detection​

  • SCAN, BIST, and serial/parallel loopback functions​