SoC Design IP and Verification IP Solutions | Cadence IPSoC Design IP and Verification IP Solutions | Cadence IPSoC Design IP and Verification IP Solutions | Cadence IP

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Go with an open IP platform and the freedom to customize your app driven SoC design

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Expert Corner

Whiteboard Wednesdays

Whiteboard Wednesdays - Low Power SoC Design with High-Level Synthesis
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Blogs

PCI-SIG DevCon 2019 APAC Tour: All Around Latest Spec Updates and Solution Offering

PCI-SIG DevCon 2019 APAC tour has come to Tokyo and Taipei this year. The focus...

Did You “Stress Test” Yet? Essential Step to Ensure a Quality PCIe 4.0 Product

The PCI-SIG finalized the PCIe 4.0 specification with doubling the data to 16GT/s from 8GT/s...