Software Development

Making Software Development Much Easier

Softwre development process

The Cadence® Tensilica® Xtensa® Software Developer's Toolkit (SDK) provides a comprehensive collection of code generation and analysis tools that speed the application software development process. Our Eclipse-based Xtensa Xplorer Integrated Development Environment (IDE) serves as the cockpit for the entire development experience.

A Perfect Match for the Hardware

The Xtensa software development environment is automatically generated from the same database as the processor hardware description. All configuration options and designer-defined TIE instructions are supported. There is no need to manually edit or extend the tools to match these options. There is no chance that a software engineer implementing a new instruction in the compiler will implement the instruction differently than the hardware engineer who wrote the instruction because there is only one unified source description. This approach assures correctness and consistency by construction.

Designers get a compiler, linker, assembler, and debugger for their particular DPU hardware. As the base Xtensa ISA is always present, third-party tools can still be used even when the core is customized for a particular application.

Xtensa Xplorer IDE

The SDK includes the Xplorer IDE, a complete GUI-based environment that helps you create application code for customized, high-performance DPUs. All the code development tools are created using the same exact database as the DPU, guaranteeing the tools are aware of all DPU configuration options and instruction extensions. Xtensa Xplorer is your interface to powerful software development tools such as the advanced Xtensa XCC compiler, the cycle and pipeline accurate ISS and TurboXim, and the multiprocessor modeling environment XTMP and XTSC for SystemC.

Xtensa Xplorer provides you a window into our software development toolchain, which consists of familiar GNU-based tools such as an optimizing compiler, assembler, linker, debugger, and code profiler. Additionally, easy-to-use source code editor and a project manager to help you create and maintain complex programming projects and eliminate the need to write and maintain makefiles. Our SDK is a complete development environment which eases the creation and testing of application code for Xtensa processors.

The Highly Efficient XCC

The centerpiece of the Xtensa compiler tool chain is the Xtensa C/C++ Compiler (XCC). XCC employs sophisticated multi-level optimizations such as function inlining, software pipelining, static single assignment (SSA) optimizations, and other code generation techniques to reduce code size and increase execution speed. It also uses advanced optimization techniques and supports operating overloading on custom data types in the C programming language (without the overhead that is often associated with it).

Our XCC C/C++ compiler supports all modifications that hardware designers can make to a Tensilica DPU. If an application needs to work on 56-bit data, a designer can define a custom 56-bit data type with a single line of code. XCC makes porting and creating C application code much easier than other compilers.

Debugger

The Debugger lets you target either the pipeline/cycle accurate Instruction Set Simulator (ISS) or TurboXim when no hardware is available or external probes need to connect with hardware development boards. The GUI-based debugger allows full system visibility into your project. It controls program execution and provides views to variables, breakpoints, memory, registers, etc. It interoperates seamlessly with the other development tools (compiler toolchain, ISS) to allow rapid code development.

DPUs in multi-processor subsystems can be debugged and stepped synchronously or asynchronously with the other cores.

Advanced Code Profiling

Code profiling is an extremely important vehicle for optimizing the performance of your application code. The Xplorer IDE lets you graphically view profiling results generated by our ISS. For much faster and accurate profiling, you can generate profiling data from hardware instantiated in an FPGA or ASIC. You can track performance data such as instruction execution count, subroutine calls, subroutine total cycles, cache performance, etc. For inner loop optimizations, the pipeline view shows any pipeline inefficiencies and bubbles that may be occurring.

Vectorization Assistant Helps You Exploit Parallelism

The Vectorization Assistant goes beyond the vectorization inherent in XCC. For instance, by eliminating aliasing that is preventing auto-vectorization, it finds and displays loops in your code that could be vectorized by XCC if the source was tweaked. It helps you find the areas in your source code that could most benefit from vectorization, saving you the tedious work of going through your code and looking at profile, assembler, and pipeline views to find the best areas.

Modeling

There are two processor models intended for your use in SoC virtual prototypes: XTensa Modeling Protocol (XTMP) for modeling in C and XTensa SystemC (XTSC) for modeling in SystemC. XTSC offers co-simulation with Verilog using its pin-level modeling capabilities. Both models are powerful additions to Tensilica's software development toolkit. Running up to 100 times faster than RTL simulators, the XTMP/XTSC environments sccelerate software development and SoC design. Both simulations give you the ability to rapidly explore SoC partitioning alternatives and hardware/software performance tradeoffs.

XTMP and XTSC allow memory modeling of both local and system memory. System memory can have programmable latencies specified for different transaction types, allowing an accurate system simulation for analyzing performance tradeoffs. Memory-mapped peripherals may be included in an XTMP/XTSC system simulation, and functions are provided to connect the DPU to peripheral devices.

An XTMP or XTSC simulation runs in a multi-threaded environment, with each processor running in its own thread. A separate debugger is connected to each core for full visibility, and core threads can be run asynchronously or synchronized through events. Another option is to run all cores in lock-step, cycle-by-cycle mode. If one core stops on a break, all cores stop until it resumes. XTMP and XTSC have many of options for implementing, controlling and displaying results of system simulations deploying multiple cores, memories, and user-defined devices.

See the Xtensa Software Developer's Toolkit for more information.