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White Papers

Explore our white papers to get informed and keep up to date on the latest Cadence® IP developments.

Design IP White Papers

Defining a New High-Speed, Multi-Protocol SerDes Architecture for Advanced Nodes
Enhancing Desktop Virtualization Platforms with Configurable IP Cores
Five Emerging DRAM Interfaces You Should Know for your Next Design
Five Key Challenges in Designing with High-Speed Analog IP
Managing Mobile SoC Design Complexity and Costs with True Multi-Protocol Multi-Link PHY
Reducing Datacenter Energy Usage Via Power-Saving IP and System Design Techniques
Rethinking Gigabit Ethernet Design
Selecting an Optimized ADC for a Wireless AFE
Six Key Considerations for Choosing the Right Analog IP
Supporting Advanced-Node FinFET SoCs with 16Gbps Multi-Protocol SerDes PHY IP

Verification IP White Papers

Accelerated VIP Verification Approaches White Paper
Analyzing and debugging SoC performance issues
Are You Losing (Out On) Your Memory: Why Memory and Storage Have Reached Their Flashpoint
How Verification IP Can Minimize LPDDR4 PHY IP Verification Complexity
Newport Media and Cadence Success Story
Power-Aware Verification Spans IC Design Cycle White Paper
STM Electronics and Cadence Success Story
Samsung Accelerated VIP Success Story
Samsung and Cadence Success Story
Tackling verification challenges with Interconnect Validator
The Importance of a Verification Strategy and Verification IP in SOC Design Technical Brief
Verification of SSIC Design Using Cadence VIP for SSIC
White Paper: Five Emerging DRAM Interfaces You Should Know for your Next Design
White paper authored by ST Microelectronics

Tensilica Processor White Papers

An Efficient, High-Performance DSP Architecture for W-CDMA Receivers
Choosing the Right DSP for High-Resolution Imaging in Mobile and Wearable Applications
Cut DSP Development Time - Use C for High-Performance, No Assembly Required
Developing High-Performance, Low-Power Audio/Voice Subsystems Using Customizable DSP Blocks and Audio Interface IP
High-Speed Alternatives for Inter-Processor Communications in SOCs
Keeping Always-On Systems On for Low-Energy Internet-of-Things Applications
Managing Multiple Wireless Standards for Smart Home Applications
Meeting Multiple IoT Application Requirements with a Single, Configurable DSP Core
Processor IP Power Specifications: A Cautionary Tale
Reduce Development Risk and Add Programmability with RTL-Like Performance and Connectivity
Selecting Your Processor or DSP IP— A Checklist
Ten Reasons to Optimize a Processor
The What, Why, and How of Customizable Processors
Virtually Unlimited I/O Bandwidth