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Explore our white papers to get informed and keep up to date on the latest Cadence® IP developments.

Enhancing Desktop Virtualization Platforms with Configurable IP Cores
Enhancing Desktop Virtualization Platforms with Configurable IP Cores
White Paper: Five Emerging DRAM Interfaces You Should Know for your Next Design
Six Key Considerations for Choosing the Right Analog IP
6 Key Considerations for Choosing the Right Analog IP
Five Key Challenges in Designing with High-Speed Analog IP
Five Key Challenges in Designing with High-Speed Analog IP
Reducing Datacenter Energy Usage Via Power-Saving IP and System Design Techniques
Virtualization and PCI Express updates contribute to reducing datacenter energy usage.
Verification of SSIC Design Using Cadence VIP for SSIC
SuperSpeed Inter-Chip (SSIC) is a “chip-to-chip” interconnect that allows users to combine USB 3.0 designs over MIPI Mobile PHY (M-PHY) to provide a high- speed and low-power interface for on-board inter-connectivity. For example, SSIC can be used to connect a mobile applications processor
to a 3G/4G baseband chip as shown in Figure 1. The applications processor could use the same, unmodified USB drivers it uses for an external USB plug-in 3G/4G modem. It uses USB 3.0 to communicate, but uses less power because of the low pin signal interface. It does not use a standard USB 3.0 cable but, instead, a different M-PHY interface for SSIC. The M-PHY interface can be shared between the low latency interface (LLI) and SSIC. Figure 1 shows a device under test, featuring a SSIC device with M-PHY …
Tackling Verification Challenges with Interconnect Validation Tool
Selecting an Optimized ADC for a Wireless AFE
This paper examines two key architectures—pipeline and successive approximation register (SAR)—that are deemed suitable for the analog-to-digital converter (ADC) that is a key component of a wireless analog front end (AFE). The paper then discusses why the SAR architecture is the most ideal of the two to meet power and performance requirements at advanced nodes.
Supporting Advanced-Node FinFET SoCs with 16Gbps Multi-Protocol SerDes PHY IP
This paper takes a look at how a new 16Gbps multi-protocol SerDes PHY IP addresses the unique challenges of advanced-node FinFET design. The paper also discusses the benefits offered by its multi-protocol capability to support SoCs for server computing applications.
Developing High-Performance, Low-Power Audio/Voice Subsystems Using Customizable DSP Blocks and Audio Interface IP
This white paper describes how customizable digital signal processing (DSP) and audio/voice subsystem solution intellectual property (IP) blocks can be used to cost-effectively and efficiently develop and deliver high-performance audio/voice products.
Defining a New High-Speed, Multi-Protocol SerDes Architecture for Advanced Nodes
Designing a high-speed, high-performance serializer/deserializer (SerDes) for advanced process nodes can be challenging on many levels. The speed (16Gbps) stresses the capabilities of even the most modern process with limited gain available and without area-intensive peaking inductors. The high channel loss (-30dB) requires a decision feedback equalization (DFE) architecture, and the low-power constraints preclude the use of speculative designs. With multiple protocols and different processes in play, it’s difficult to optimize for a single set of requirements; this situation instead calls for more general solutions.
Analyzing and Debugging Performance Issues with Advanced ARM CoreLink System IP Components
Are You Losing (Out On) Your Memory: Why Memory and Storage Have Reached Their Flashpoint
Power-Aware Verification Spans IC Design Cycle White Paper
Accelerated VIP Verification Approaches White Paper
Accelerated VIP Verification Approaches White Paper
Samsung Accelerated VIP Success Story
Samsung Accelerated VIP Success Story
White paper authored by ST Microelectronics
ST Microelectronics HDMI 2.0 verification white paper
An Efficient, High-Performance DSP Architecture for WCDMA Receivers
This whitepaper begins with a comprehensive summary of the algorithms for WCDMA (Wideband Code Division Multiple Access) modem systems. This is followed by a detailed description of how the WCDMA algorithms can be implemented using Tensilica DSP cores and programmable accelerators for a WCDMA system. Finally, a use case is given on easily updating an existing LTE/LTE-Advanced modem system to become a multi-standard 3G/WCDMA system.
Seven Critical Questions to Ask When Selecting a Digital Audio Solution for Your Next Mobile SOC Design
The complexity of delivering a mobile audio IP solution to SOC designers causes design teams to ask many, many questions before choosing an audio core and associated codecs. That's a good thing. The selection process is complex, and the more information you have before making the decision, the better. Experience shows that design teams' questions about mobile audio solutions fall into seven broad categories.
Five Emerging DRAM Interfaces You Should Know for your Next Design
Producing DRAM chips in commodity volumes and prices to meet the demands of the mobile market is no easy feat, and demands for increased bandwidth, low power consumption, and small footprint don’t help. This paper reviews and compares five next-generation DRAM technologies—LPDDR3, LPDDR4, Wide I/O 2, HBM, and HMC—that address these challenges.
Analyzing and debugging SoC performance issues
Analyzing and debugging SoC performance issues
Newport Media and Cadence Success Story
The Importance of a Verification Strategy and Verification IP in SOC Design Technical Brief
STM Electronics and Cadence Success Story
Samsung and Cadence Success Story
Tackling verification challenges with Interconnect Validator
Tackling verification challenges with Interconnect Validator
Put Low-Power, Low-Overhead, High-Fidelity Digital Sound in Your Next ASIC or SOC
This paper explains the benefits of using a programmable processor-based solution for audio processing in SOC designs, as well as the disadvantages of using a RISC or other general-purpose core. It explains the 300 audio-specific instructions added to make the HiFi 2 Audio DSP much more efficient than a standard RISC processor to handle audio processing tasks.