SoC Verification and Simulation IP | Cadence IP

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Verification IP

Why Is VIP Important?

The SoC development process typically requires months of digital simulation effort to verify the functional performance of an SoC before taping out the design. In fact, simulation will usually continue after tapeout and up till the time that silicon is received back from the lab. The reason for this extended effort is that functional verification is never finished! SoCs are simply too complex for the logical design to ever be 100% verified. Recognizing that verification is never finished, leading SoC developers make every effort to improve the efficiency of the verification process to complete more verification cycles before taping out a chip.

One of the most time consuming aspects of SoC verification is creating a testbench that models the SoC's interfaces. Since a typical SoC contains dozens of interfaces such a DDR, USB, PCI Express, etc., modeling all those interfaces is extremely time consuming. Cadence® VIP provides a huge benefit by modeling all those interfaces as components that can be plugged in to an SoC testbench and simulated along with the chip.

The use of VIP not only saves man-months of development time, it also frees up valuable talent. SoC interface protocols can be very complex with specifications that are hundreds of pages long. There are usually very few protocol experts in a company. Using off-the-shelf VIP frees up those valuable resources for other work. VIP helps you benefit from the experience of others. It incorporates lessons learned from a wide range of projects across many different design applications.

What's Unique About Cadence VIP?

A Proven Solution, the S.M.A.R.T. Choice

A Proven Solution

Cadence has been focused on developing the best VIP on the market for over a decade. To date, over 500 customers have used our VIP to verify thousands of designs. All that experience results in a refined product you can trust to verify your next design. Even new protocols benefit from this long evolution since most new protocols are evolutions of preceding versions. 

Looking forward, Cadence actively participates in more than 20 standards organizations to help develop new interface protocols and have VIP ready when early-adopters start their designs.

The S.M.A.R.T. Choice

Cadence VIP is the smart choice for your next project based on five unique capabilities:

SoC-level verification power

  • Boost simulation performance by 100X and more using Accelerated VIP with the Palladium® XP series of hardware accelerators
  • Verify conformance with SoC interconnect IP rules using Interconnect Validator
  • Enable SoC latency and bandwidth analysis with Interconnect Workbench

Memory support

  • Verify all your memory interfaces with Memory Models spanning:
    • 6000 memory components
    • 60 types of memory interfaces
    • 85 memory manufacturers

Availability of protocols

  • Verify all the complex interfaces in your design with Interface VIP covering more than:
    • 40 communication protocols
    • 60 memory interfaces
  • Leverage the outstanding Cadence track record of being first to market with support for new protocols

Ready-made for your environment

  • Maximize the value of your simulation licenses, and get consistent results whether you use Cadence Incisive, Synopsys VCS, or Mentor Questa
  • Choose and use your preferred verification language, whether it's SystemVerilog, e, Verilog, VHDL, or C/C++
  • Migrate to the Universal Verification Methodology (UVM) or continue using the legacy methodologies that preceded it. It's your choice!

Technically advanced features

  • Perform superior protocol compliance verification with TripleCheck IP Validator
  • Shorten time-to-first test with the PureView graphical configuration utility
  • Use available Assertion-Based VIP for exhaustive formal verification of parallel bus protocols

Why Are There Different Types of VIP?

Verifying an SoC is a complex and challenging task that requires multiple approaches. Cadence provides VIP that makes each approach more efficient and more effective.

Explore the various types of VIP

Simulation VIP is used in digital logic simulation. This is the workhorse of SoC verification and involves the use of digital logic simulations such as Cadence Incisive® Simulator, Synopsys VCS, or Mentor Questa. Simulation has reached a high level of sophistication with special languages (primarily SystemVerilog and e) being used to achieve a high level of engineering efficiency. 

Memory Models take the place of memory components in digital simulation. They provide similar functionality to simulation VIP but are used to model specific components instead of generic devices. This enables them to accurately timing and device-specific behavior.

Accelerated VIP makes hardware-assisted verification easier and more productive. Hardware-assisted verification is an approach that uses special-purpose computing hardware to offload some or all the work from a logic simulator and perform verification much faster than is otherwise possible.

Assertion-Based VIP is used in formal analysis—a mathematical approach to verification that has the unique ability to prove that a design is 100% correct. Assertion-Based VIP makes it easy to perform formal analysis on designs with standard interfaces.

Productivity Tools are provided to boost engineering efficiency. These products complement the other types of verification VIP

Interconnect Solution comprises VIP and tools specifically targeted to verify SoCs incorporating sophisticated interconnect IP. The products enable functional verification and also SoC performance analysis.

Explore VIP Solutions

Visit the Resource Pages to learn about MIPI and PCI Express resources.