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Advanced Node DDR4 PHY IP

Future Proof Your SoC Now!

Cadence® Denali® DDR4 PHY IP in 16nm FinFET (16FF) is the latest in a more than a 10-year history of silicon-proven PHY IPs. It is designed to meet the maximum performance of the DDR4 standard, which is specified to scale up to 3200Mbps, and is backward compatible with earlier DDR3 and DDR4 specifications with maximum speeds of 2133Mbps.

Cadence DDR4 PHY IP targets the microserver market – low-power servers that have small demands on compute power but high demands on moving high numbers of data traffic. Other markets include equipment used in enterprise datacenters – servers, network switches, storage fabric, and other SoC designs that require high-memory bandwidth in a leading-edge process.

Cadence design innovations support the increase in bandwidth and insure the reliability of the design.

Key Features

Key Innovations