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Simulation VIP

Verification IP (VIP) for simulating SoC Interfaces such as USB, PCI Express, Ethernet, MIPI, DDR, AMBA AXI, AMBA AHB, and AMBA ACESimplify Digital Simulation of Standard Interfaces

Cadence® Simulation VIP is the world's most widely used VIP for digital simulation.  Hundreds of customers have used Cadence VIP to verify thousands of designs, from IP blocks to full systems on chip (SoCs).  

The Simulation VIP is ready-made for your environment, providing consistent results whether you are using Cadence Incisive®, Synopsys VCS®, or Mentor Questa® simulators.  You have the freedom to build your testbench using any of these verification languages: SystemVerilog, e, Verilog, VHDL, or C/C++.  Cadence Simulation VIP supports the Universal Verification Methodology (UVM) as well as legacy methodologies.  

The unique flexible architecture of Cadence VIP makes this possible.  It includes a multi-language testbench interface with full access to the source code to make it easy to integrate VIP with your testbench.  Optimized cores for simulation and simulation-acceleration allow you to choose the verification approach that best meets your objectives.

More than a BFM

People sometimes think of VIP as just a bus functional model (BFM) that responds to interface traffic.  But SoC verification requires much more than just a BFM. Cadence Simulation VIP components deliver:

State machine models

State machine models implement the protocol communication defined in an interface specification. These are fundamental for any VIP component and are sometimes referred to as bus function models, or BFMs.  Cadence VIP components differ from ordinary BFMs because they thoroughly model the subtle features of state machine behavior, such as support for multi-tiered, power-saving modes found in the latest versions of many protocols.

USB LTSSM State Machine

USB 3.0 LTSSM State Machine

Protocol checks

Protocol checks are a key VIP feature.  These are pre-programmed assertions that are built into the VIP to continuously watch simulation traffic to check for protocol violations.  When a violation is encountered, an error message is logged for subsequent analysis.  Cadence VIP components often incorporate hundreds of protocol checks.  It’s like having a protocol expert check your simulation results.

Protocol Check Example

Example Protocol Checks from USB 3.0 VIP

Test suite

Test suites are provided for most Cadence VIP components.  While protocol checks are essential, they will only detect a bug if the right sequence of events occurs that will expose the bug.  Basic test suites are provided for most of our VIP, and comprehensive test suites are provided for the most complex and error-prone protocols.

Coverage model

Coverage models are pre-programmed scoreboards used to capture interesting combinations of simulation results.  In SystemVerilog terminology, a set of covergroups would comprise the coverage model.  For example, a USB coverage model may include a covergroup that captures the combination of address, endpoint number and direction for each data transfer that occurs during a simulation run.  By analyzing the results collected by the coverage model, engineers can tell if the simulations have exercised the various modes of operation of an interface.

Verification plan

Verification plans are a complement to coverage models. Since interface protocols are typically very complex and may require hundreds of covergroups to capture all the significant behavior, it can be very difficult to relate the coverage model results back to the protocol specification.  Verification plans link the “raw” coverage model results back to the protocol specification. This way, you can tell if all the requirements of a protocol specification have been covered.  The Incisive Enterprise Manager tool in our Incisive simulator provides a convenient cockpit for visualizing coverage model results mapped into the VIP verification plans. Verification plans are available in XML format so you can import them into third-party simulation environments.

Portfolio

VIP PortfolioA great choice for VIP needs that change over time

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SoC PortfolioA cost effective way to incorporate multiple VIP in the same simulation

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ARM AMBA

AMBA 5 CHI Simulation VIPPart of a complete CHI verification solution

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AMBA 4 ACE Simulation VIPThe first and most widely used ACE VIP

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AMBA 4 Stream Simulation VIPAchieve continued success with next-generation designs

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AMBA AHB Simulation VIPProven on hundreds of chip design projects

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AMBA AXI Simulation VIPThe most widely used AMBA AXI VIP

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Display

DisplayPort Simulation-VIPSupports DisplayPort and embedded DisplayPort

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HDMI 1.4 Simulation VIPFeatures optional Accelerated VIP

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HDMI 2.0 Simulation VIPThe first VIP to support HDMI 2.0

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Mobile High-Definition Link (MHL) Simulation VIPSupports 24bits and 16bits per pixel mode

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Ethernet

Ethernet 10/100/1G/10G Simulation VIPBroadest range of MAC interface support

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Ethernet 40G/100G Simulation VIPSupports Energy Efficient Ethernet (EEE)

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Ethernet 25G/50G Simulation VIP25Gbps/50Gbps speeds for MAC-PHY, PHY sub-layers, and TX-RX stations

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MIPI

MIPI CSI-2 Simulation VIPIn production since 2008 on dozens of production designs

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MIPI CSI-3 Simulation VIPIncludes the MIPI M-PHY and UniPro VIP

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MIPI C-PHY Simulation VIPFirst to market with C-PHY VIP support

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MIPI D-PHY Simulation VIPIndustry's first D-PHY VIP

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MIPI DigRF Simulation VIPThe first VIP to support DigRF

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MIPI DSI Simulation VIPIn production since 2008 on dozens of production designs

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MIPI LLI Simulation VIPThe world's first LLI VIP

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MIPI M-PHY Simulation VIPFirst production M-PHY VIP

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MIPI SLIMbus Simulation VIPUsed on dozens of MIPI verification projects

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MIPI Soundwire Simulation VIPFirst to market with SoundWire VIP support

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MIPI UniPro Simulation VIPIndustry's first UniPro VIP

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Other

CAN Simulation VIPSupports STANDARD and EXTENDED CAN format

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I2C Simulation VIPSupports both multi-mastering and any number of slaves

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JTAG Simulation VIPProvides JTAG and cJTAG support

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LIN Simulation VIPSupports various types of predefined sequences

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OCP 2.2 Simulation VIPUsed on over 100 design projects

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OCP 3.0 Simulation VIPFirst VIP to support OCP 3.0

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PCI Simulation VIPSupports both 32- and 64-bit bus data widths

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PLB 6 Simulation VIPThe leading VIP for PLB designs

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SAS 6G Simulation VIPUsed to verify leading hard disk controllers

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SAS 12G Simulation VIPProduction proven verification capability

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SATA 6G Simulation VIPTrusted by dozens of customers

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SRIO Simulation VIPIncludes Rapid IO support

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SRIO 3.0 Simulation VIPSupport for 64b/67b encoding

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UART Simulation VIPCompatible with industry-standard UART 16550

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PCI Express

PCI Express Gen2 Simulation VIPThe most mature PCIe VIP, used by more than 100 customers

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PCI Express Gen3 Simulation VIPThe most complete and capable PCIe 3.0 VIP

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PCI Express Gen4 Simulation VIPFirst VIP to provide support for PCIe Gen4

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PCIe SR-IOV Simulation VIPSupports access to PF EROM

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PCIe MR-IOV Simulation VIPIndustry's first MR-IOV VIP

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Mobile PCI Express Simulation VIPFirst VIP to support Mobile PCI Express

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NVM Express Simulation VIPWorld's first NVM Express VIP

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USB

USB 2.0 Simulation VIPPart of a complete USB verification solution

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USB 3.0 Simulation VIPIncudes support for OTG 3.0

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SSIC Simulation VIPThe first SuperSpeed Inter-Chip VIP

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