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Simulation VIP

Verification IP (VIP) for simulating SoC Interfaces such as USB, PCI Express, Ethernet, MIPI, DDR, AMBA AXI, AMBA AHB, and AMBA ACESimplify Digital Simulation of Standard Interfaces

Cadence® Simulation VIP is the world's most widely used VIP for digital simulation.  Hundreds of customers have used Cadence VIP to verify thousands of designs, from IP blocks to full systems on chip (SoCs).  

The Simulation VIP is ready-made for your environment, providing consistent results whether you are using Cadence Incisive®, Synopsys VCS®, or Mentor Questa® simulators.  You have the freedom to build your testbench using any of these verification languages: SystemVerilog, e, Verilog, VHDL, or C/C++.  Cadence Simulation VIP supports the Universal Verification Methodology (UVM) as well as legacy methodologies.  

The unique flexible architecture of Cadence VIP makes this possible.  It includes a multi-language testbench interface with full access to the source code to make it easy to integrate VIP with your testbench.  Optimized cores for simulation and simulation-acceleration allow you to choose the verification approach that best meets your objectives.

More than a BFM

People sometimes think of VIP as just a bus functional model (BFM) that responds to interface traffic.  But SoC verification requires much more than just a BFM. Cadence Simulation VIP components deliver:

State machine models

State machine models implement the protocol communication defined in an interface specification. These are fundamental for any VIP component and are sometimes referred to as bus function models, or BFMs.  Cadence VIP components differ from ordinary BFMs because they thoroughly model the subtle features of state machine behavior, such as support for multi-tiered, power-saving modes found in the latest versions of many protocols.

USB LTSSM State Machine

USB 3.0 LTSSM State Machine

Protocol checks

Protocol checks are a key VIP feature.  These are pre-programmed assertions that are built into the VIP to continuously watch simulation traffic to check for protocol violations.  When a violation is encountered, an error message is logged for subsequent analysis.  Cadence VIP components often incorporate hundreds of protocol checks.  It’s like having a protocol expert check your simulation results.

Protocol Check Example

Example Protocol Checks from USB 3.0 VIP

Test suite

Test suites are provided for most Cadence VIP components.  While protocol checks are essential, they will only detect a bug if the right sequence of events occurs that will expose the bug.  Basic test suites are provided for most of our VIP, and comprehensive test suites are provided for the most complex and error-prone protocols.

Coverage model

Coverage models are pre-programmed scoreboards used to capture interesting combinations of simulation results.  In SystemVerilog terminology, a set of covergroups would comprise the coverage model.  For example, a USB coverage model may include a covergroup that captures the combination of address, endpoint number and direction for each data transfer that occurs during a simulation run.  By analyzing the results collected by the coverage model, engineers can tell if the simulations have exercised the various modes of operation of an interface.

Verification plan

Verification plans are a complement to coverage models. Since interface protocols are typically very complex and may require hundreds of covergroups to capture all the significant behavior, it can be very difficult to relate the coverage model results back to the protocol specification.  Verification plans link the “raw” coverage model results back to the protocol specification. This way, you can tell if all the requirements of a protocol specification have been covered.  The Incisive Enterprise Manager tool in our Incisive simulator provides a convenient cockpit for visualizing coverage model results mapped into the VIP verification plans. Verification plans are available in XML format so you can import them into third-party simulation environments.

VIP Portfolio A great choice for VIP needs that change over time

The VIP Portfolio provides the most cost-effective solutions to meet your changing verification requirements.

The VIP Portfolio provides access to all of the VIP shown in the table below.  A single VIP Portfolio license enables multiple instances of a single type of VIP in a single simulation session. Multiple licenses are needed to enable multiple VIP types in a single simulation session or multiple simultaneous simulation sessions.


The VIP Portfolio:
AMBA® AHB™ (includes APB™, AHB ABVIP, and APB ABVIP)
AMBA AXI™ 3,4  (includes APB, AXI ABVIP, and APB VIP)
AMBA4 ACE™ ABVIP
CAN
Ethernet 10/100/1G/10G
HDMI 1.3, 1.4
I2C
JTAG
LIN
MIPI CSI-2
MIPI D-PHY
MIPI DSI
OCP 2.2
OCP ABVIP
PCI Express 1.1, 2.0
PCI
PLB6
SAS 1.5G, 3G, 6G
SATA 1.5G, 3G, 6G
Serial RapidIO
SR-IOV  
USB 2.0 / OTG

SoC Portfolio A cost effective way to incorporate multiple VIP in the same simulation

The SoC Portfolio provides the most cost-effective way to support SoC-level verification incorporating multiple VIP components.

The SoC Portfolio provides access to all the VIP shown in the table below.  A single license enables multiple instances of all the VIP in a single simulation session. Multiple licenses are needed to enable multiple simultaneous simulation sessions.


The SoC Portfolio Includes:
AMBA AHB (includes APB, AHB ABVIP, and APB ABVIP)
AMBA AXI 3,4  (includes APB, AXI ABVIP, and APB VIP)
AMBA4 ACE ABVIP
CAN
Ethernet 10/100/1G/10G
HDMI 1.3, 1.4
I2C
JTAG
LIN
MIPI CSI-2
MIPI D-PHY
MIPI DSI
OCP 2.2
OCP ABVIP
PCI Express 1.1, 2.0
PCI
PLB6
SAS 1.5G, 3G, 6G
SATA 1.5G, 3G, 6G
Serial RapidIO
SR-IOV  
USB 2.0 / OTG

AMBA 5 CHI Simulation VIP Part of a complete CHI verification solution

Specification Support

The CHI VIP supports the AMBA® CHI Protocol.

Product Highlights

  • Supports link, network and protocol layer communication, including flow control mechanisms, across all RnX-to-HnX and HnX-to-SnX links
  • Models the cache in RnF-to-HnF link
  • Each link can take the part of either node as an active agent generating requests/snoops and responding according to the requests sent its way, or as a passive agent monitoring protocol correctness and collecting functional coverage

Key Features

FEATURE NAME

 DESCRIPTION

Supports all protocol transaction types

Supports monitoring and driving of all protocol Opcodes, including barrier, exclusive access, and DVM.

Active HN-F which mimics a CHI based interconnect Active HN-F, which generates snoop requests and response to RN-F commands (when interconnect is not present).
Supports link, network and protocol layer communication

Support all type of interfaces

Support for Rn-F/Rn-D/Rn-I to Hn-F/Hn-D/Hn-I/Mn and Hn-F/Hn-I/Mn to Sn-F/Sn-I

Flow control mechanisms.

Available across all RnX-to-HnX and HnX-to-SnX links

Support delays on all channels

Users can delay the driving of each protocol flit.

VIP contains cache model

Facilitates the role of actual cache used in an CHI RN.

Cache Backdoor accesses

Insert-specific or random values can be sent to the cache at the beginning of a test or during run time.

Supported Design-Under-Test Configurations

Home Node Request Node
Slave Node Miscellaneous Node

Test Suite Options

Basic CMS PureSuite TripleCheck

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

AMBA 4 ACE Simulation VIP The first and most widely used ACE VIP

Specification Support

The ACE VIP supports the AMBA® ACE Protocol V1.0 and V2.0. It extends the AXI VIP which supports the AMBA® AXI Protocol v1.0 and v2.0 and the AXI as defined in the AMBA AXI Protocol Specification.

Product Highlights

Key Features

Feature Name
Description
ACE Lite support Allows ACE Lite configuration; automatically modify the agent accordingly
All data and address widths Supports all legal data and address widths
AXI support Supports the entire AXI spec. All AXI transactions can be sent and monitored
Automatic slave responses Configurable option to use automatic slave responses
Barrier transactions Supports monitoring and driving of barrier transactions
Cache model Cache model in both active and passive agents including cache state checks
Controlling order in channels Supported
Data before address mode Supports sending of data before address transactions when legal
Delay control on all channels Sets the delay between the items on the channels
DVM transactions Supports monitoring and driving of DVM transactions
Exclusive access Supports monitoring and driving of all exclusive transactions
Locked transactions Supports monitoring and driving of locked transactions
Low-power interface support Supports both LPI controller and LIP peripheral agents
Master burst signals control Determines the values of the signals in the read and write address channel
Master transfer signals control Determines the values of the signals in the write data channel
Master snoop response control Determines the values of the signals in the snoop response channel
Master snoop signals control Determines the values of the signals in the snoop address channel
Multiple agents support Can support any number of agents
Read-only and write-only interfaces  Supported
Slave response control Determines the values of the signals in the read data channel
Snoop filter support Supports connection to a snoop filter
Supports all protocol transaction types Supports monitoring and driving of all read and write transactions

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full stack Controller-only PHY-only

Test Suite Options

Basic CMS PureSuite TripleCheck

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

User Feedback

"Delivering advanced multi-core ARM SoCs to our customers requires leading IC design technologies. Cadence VIP for AXI4 and ACE enables us to quickly and efficiently deliver bug-free SoC designs."

– Ting Lei, Director of Cloud Computing, HiSilicon

"As the complexity of ARM partners’ designs increases year after year, successfully verifying the performance of the SoCs has become a critical imperative. The comprehensive Cadence verification IP solution for AMBA protocols has enabled our mutual customers to address this challenge while incorporating the latest ARM technology."

– Joe Convey, Director of Design Enablement, ARM

AMBA 4 Stream Simulation VIP

Specification Support

The AXI4-Stream VIP supports the AMBA AXI4-Stream Protocol v1.0 and the AXI4-Stream as defined in the AMBA AXI4-Stream Protocol Specification.

Key Features

Feature Name
Description
All data and address widths Customizable address and data width up to 32 bits
Controlling order in the interface Order in the interface is fully controllable by the user
Delay control Sets the delay between the items on the interface
Master packet signals control Determines the values of the signals in the interface
Master transfer signals control Determines the values of the signals in the write data channel
Multiple agents support Can support any number of agents

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full stack Controller-only PHY-only

Test Suite Options

Basic CMS PureSuite TripleCheck

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

User Feedback

“As the complexity of ARM partners’ designs increases year after year, successfully verifying the performance of the SoCs has become a critical imperative. The comprehensive Cadence verification IP solution for AMBA protocols has enabled our mutual customers to address this challenge while incorporating the latest ARM technology. ARM’s partnership with Cadence helps customers achieve continued success as they roll out next-generation designs incorporating our most advanced AMBA specifications such as AXI4 and AXI Coherency Extensions (ACE).” 
–Joe Convey, Director of Design Enablement, ARM

AMBA AHB Simulation VIP Proven on hundreds of chip design projects

Specification Support

The AHB VIP supports the AMBA AHB Protocol v1.0 and v2.0 and the AMBA AHB-Lite Protocol v1.0 and the AHB as defined in the AMBA AHB Protocol Specification.

Product Highlights

Key Features

Feature Name
Description
All data and address widths Supports all legal data and address widths
Automatic slave responses Configurable option to use automatic slave responses
Delay control on all channels Sets the delay between the items on the channels
Master burst signals control Determines the values of the signals in the read and write address channel
Master transfer signals control Determines the values of the signals in the write data channel
Memory monitoring  Memory can be set using backdoor access
Multiple agents support Can support any number of agents
Random error injection Easy testing of error scenarios
Slave response control Determines the values of the signals in the read data channel
Slave memory emulation  Supported
Supports all protocol transaction types Supports monitoring and driving of all read and write transactions
Transaction tracker Configurable tracking of all the transactions on the channels
Support for Hunalign and Hstrb  Supported
Support all slave's responses Supports OKAY, ERROR, SPLIT, and RETRY 
Support Lite cortex M3 Support retraction as defined in cortex M3 spec

 

Supported Design-Under-Test Configurations

Master Slave Decoder
Arbiter    

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

AMBA AXI Simulation VIP The most widely used AMBA AXI VIP

Specification Support

The AXI VIP supports the AMBA AXI Protocol v1.0 and v2.0 and the AXI as defined in the AMBA AXI Protocol Specification.

Product Highlights
  • The most widely used AXI VIP

Key Features

Feature NameDescription
All data and address widths Supports all legal data and address widths
AXI4 additional signaling Supports AxQOS, AxREGION, and user-defined signals
AXI4 Lite support Allows AXI4 Lite configuration; automatically modifies the agent accordingly
Automatic slave responses Configurable option to use automatic slave responses
Controlling order in channels  Supported
Data before address mode Supports sending of data before address transactions when legal
Delay control on all channels Sets the delay between the items on the channels
Exclusive access Supports monitoring and driving of all exclusive transactions
Locked transactions Supports monitoring and driving of locked transactions
Low power interface support Supports both LPI controller and LIP peripheral agents
Master burst signals control Determine the values of the signals in the read and write address channel
Master transfer signals control Determines the values of the signals in the write data channel
Multiple agents support Can support any number of agents
Read-only and write-only interfaces Supported
Slave response control Determines the values of the signals in the read data channel
Supports all protocol transaction types Supports monitoring and driving of all read and write transactions

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full stack Controller-only PHY-only

 

Test Suite Options

Basic CMS PureSuite TripleCheck

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

User Feedback

“HiSilicon is a leader in ASICs and solutions for communication networks and digital media. Delivering advanced multi-core ARM SoCs to our customers requires leading IC design technologies. The Cadence VIP for AXI4 and ACE enables us to quickly and efficiently deliver bug-free SoC designs.” 
– Ting Lei, Director of Cloud Computing, HiSilicon

CAN Simulation VIP

Specification Support

This VIP supports specification versions:  2.0 and 1.0

Key Features

Feature Name
Description

CAN FD

Supports Flexible Data Rate

CAN formats

Supports STANDARD and EXTENDED CAN format

CAN frames

Supports data, remote, error, and overload frames

Configurable agents

Supports multiple CAN agent instantiations

Error frames

Supports generation of frames with errors in particular fields, such as CRC, delimiters, EOF

Fault confinement

Tracks error counters and fault states

ISO 16485 conformance test

Supports ISO 16485 conformance test regression suite

Response for DATA frames

Supports generation of DATA frames in response to a REMOTE frame with a particular ID

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full stack Controller-only PHY-only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

 

DisplayPort Simulation-VIP Supports DisplayPort and embedded DisplayPort

Specification Support

This VIP supports specification versions: DisplayPort 1.2 and Embedded DisplayPort (eDP) versions 1.3 and 1.4. 

Key Features

Feature Name
Description
DisplayPort 1.2

AUX

Supports Native AUX and I2C-over-AUX
Enables AUX Manchester-II encoding, start and stop conditions
Provides support for AUX jitter generation and detection

Bit depth

Handles all pixel bit widths

DPCD Provides support for DisplayPort Configuration Data (DPCD) v1.2
ECC Supports secondary data error correcting code (ECC)
Enhanced framing Supports both basic framing as well as enhanced framing with increased robustness
HPD Supports HPD plug, unplug, hot plug, and IRQ
Link quality test Supports link quality measurement patterns: Nyquist, Symbol Error Rate, PRBS7, Custom 80 Bit, and HBR2 EYE pattern

Link rate

Models High Bit Rate 2 (HBR2) 5.4Gbps, High Bit Rate (HBR) 2.7Gbps, and Reduced Bit Rate (RBR) 1.62Gbps modes

Link training

Full link training and status monitor, including clock recovery and channel equalization sequences
Adjustable link rates, drive voltage swing levels, and pre-emphasis levels
Enables link re-training on loss of clock lock, symbol lock, or inter-lane alignment
Main link link layer Supports isochronous transport services in Single Stream Transport (SST) mode

Main link physical layer

Provides main link scrambling and de-scrambling, ANSI 8B10B encoding/decoding, serialization, and deserialization

MSA/SDP

Enables insertion and verification of Main Stream Attributes (MSA) and Secondary Data Packet (SDP)
Number of main link lanes Supports x1, x2, and x4 lane configurations
Power management Enables sink power state machine and power-save mode
eDP 1.3
Backlight control Enables backlight and display control registers
Display authentication Supports Alternative Scrambler Seed Reset (ASSR)

Fast training

Supports fast training without AUX handshakes
PSR Provides the ability for Panel Self Refresh (PSR)
eDP 1.4
ALPM Supports Advanced Link Power Management (ALPM) to reduce wake latency

Link rate

Supports new standard link rates: R216 (2.16Gbps), R243 (2.43Gbps), R324 (3.24Gbps), and R432 (4.32Gbps) for system optimization
Voltage swing Supports increased voltage swing range, allowing lower swing levels

Supported Design-Under-Test Configurations

Source Sink Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

Ethernet 10/100/1G/10G Simulation VIP Broadest range of MAC interface support

Specification Support

This VIP supports MII, RMII, SMII, GMII, TBI, RTBI, RGMII, SGMII, 1GBASE-TX, XGMII, XAUI, XSBI, 10GBASE-KX4, and 10GBASE-KR interfaces.

The Ethernet specifications are developed and maintained by IEEE.

Product Highlights

  • Supports broadest range of MAC interfaces
  • Supports Energy-Efficient Ethernet, Priority-based Flow Control, and Ethernet Audio/ Video 
  • Provides automotive Ethernet support 
  • Features optional Accelerated VIP

Supported Interfaces

Interface
Supported speed and Duplex Kind
MII

10/100Mbps(Half/Full Duplex)

RMII

10/100Mbps(Half/Full Duplex)

SMII

10/100Mbps(Half/Full Duplex)

GMII

1Gbps(Half/Full Duplex)

TBI

 1Gbps(Half/Full Duplex)

RTBI

1Gbps(Half/Full Duplex)

1000BASEKX

1Gbps(Half/Full Duplex)

RGMII

10/100Mbps and 1Gbps(Half/Full Duplex)

SGMII

10/100Mbps and 1Gbps(Half/Full Duplex)

QSGMII

10/100Mbps, 1Gbps 4 independent ports(Half/Full Duplex)

XGMII

10Gbps(Full Duplex only)

XSBI

10Gbps(Full Duplex only)

Xaui

10Gbps(Full Duplex only)

RXAUI

10Gbps(Full Duplex only)

TENGKX4

10Gbps(Full Duplex only)

TENGKR

10Gbps(Full Duplex only)

 

Key Features

Feature

Description

Custom CRC

User-configurable CRC field

No Preamble

Option to send an Ethernet Packet without Preamble, supported for limited interfaces

Priority pause-based Flow Control (PFC)

Link level flow control for each Class of Service (CoS) as defined by IEEE P802.1p

Pause frame based flow control

Flow control mechanism in which overwhelmed network element sends a pause frame which halts the transmission for a specified period of time

Forward Error Correction (FEC)

FEC appends to the Ethernet frame, additional data that is a result of set of non-binary arithmetic functions performed on the data of the Ethernet frame. This additional data (known as the FEC parity octets) is used to correct errors at the receiving end of the link that may occur when the data is transferred through the link.

Energy Efficient Ethernet (EEE)

EEE is a set of enhancements to the twisted-pair and backplane Ethernet family of computer networking standards that will allow for less power consumption during periods of low data activity as per Standard IEEE 802.3az

Management Data Input/Output (MDIO)

Serial bus defined for Ethernet family PHY read and write registers

Proprietary header

Allows custom field insertion anywhere inside the frame starting from the SFD field to the CRC field

Custom VLAN

Allows customization of VLAN tags

Custom CRC length

Allows configuration of number of bytes in a CRC field

Clause-37 Auto-negotiation

Auto-negotiation of 1000BASEX PHYs

Clause-73 Backplane Auto-negotiation

Auto-negotiation for Ethernet backplane interfaces

Custom message

Allows insertion of a message inside the Ethernet frame

Custom Preamble

Custom preamble replaces the standard preamble of seven bytes and Start Frame Delimiter with a random pattern header of n number of bytes, where n is configurable

Operational Mode

 Active, Passive configuration

Supported frame types

802.3, MAGIC, JUMBO, PAUSE, PFC-PAUSE, VII, SNAP
Tagged frame - single tagged (Q-VLAN tag), double tagged (S-VLAN tag and Q-VLAN tag)

Speed of operation

10Mbps, 100Mbps, 1Gbps, 10Gbps

Start-up protocol with link training support

PMD link training as described in Clause 72 of IEEE 802.3

 

MacSec GCM-AES-256/128

Ethernet frames can be encrypted/decrypted with a user-defined 256/128-bit secure association key based on default cipher suites GCM-AES-256/128. Frames can be integrity or confidentiality protected.

802.1qav based Credit Based Shaper Algorithm Support

802.1qav based Credit Based Shaper Algorithm support for Time Sensitive Streams using QVLAN Enabled packets for all ENET Interfaces.

Supported Design-Under-Test Configurations

MAC PHY Hub/Switch
Full stack Controller-only PHY-only

Test Suite Options

Basic CMS PureSuite TripleCheck

(CMS only available for 10G interfaces) 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

Ethernet 40G/100G Simulation VIP Supports Energy Efficient Ethernet (EEE)

Specification Support

This VIP supports Autonegotiation, PMD Link Training, FEC, EEE, 25G MAC support, 40GBASE-R, CGMII, and 100GBASE-R interfaces.

The Ethernet specifications are developed and maintained by IEEE.

IEEE standards are accessible to registered users at: http://www.ieee802.org/3/.

Product Highlights

  • Supports broadest range of MAC interfaces
  • Supports Energy-Efficient Ethernet, Priority-Based Flow Control, and Ethernet Audio/ Video 
  • Optional TripleCheck product provides pre-silicon compliance tests for 40G/100G verification

Supported Interfaces

Interface
Supported speed and Duplex Kind
MII 10/100Mbps(Half/Full Duplex)
RMII 10/100Mbps(Half/Full Duplex)
SMII 10/100Mbps(Half/Full Duplex)
GMII 1Gbps(Half/Full Duplex)
TBI  1Gbps(Half/Full Duplex)
RTBI 1Gbps(Half/Full Duplex)
1000BASEKX 1Gbps(Half/Full Duplex)
RGMII 10/100Mbps and 1Gbps(Half/Full Duplex)
SGMII 10/100Mbps and 1Gbps(Half/Full Duplex)
QSGMII 10/100Mbps, 1Gbps 4 independent ports(Half/Full Duplex)
XGMII 10Gbps(Full Duplex only)
XSBI 10Gbps(Full Duplex only)
Xaui 10Gbps(Full Duplex only)
RXAUI 10Gbps(Full Duplex only)
TENGKX4 10Gbps(Full Duplex only)
TENGKR 10Gbps(Full Duplex only)
20GBASER 20Gbps(Full Duplex only)
40/100G CGMII 40/100Gbps(Full Duplex Only)
40GBASER/100GBASER 40/100Gbps(Full Duplex Only)


Key Features

Feature
Description
Custom CRC User-configurable CRC field
No preamble Option to send an Ethernet packet without preamble, supported for limited interfaces
Priority pause-based flow control (PFC)

Link-level flow control for each class of dervice (CoS) as defined by IEEE P802.1p

Pause frame-based flow control

Flow control mechanism in which overwhelmed network element sends a pause frame which halts the transmission for a specified period of time

Forward Error Correction (FEC) FEC appends to the Ethernet frame additional data that is a result of a set of non-binary arithmetic functions performed on the data of the Ethernet frame. This additional data (known as the FEC parity octets) is used to correct errors at the receiving end of the link that may occur when the data is transferred through the link.
Energy-Efficient Ethernet (EEE) EEE is a set of enhancements to the twisted-pair and backplane Ethernet family of computer networking standards that allow for less power consumption during periods of low data activity, per Standard IEEE 802.3az
Management Data Input/Output (MDIO) Serial bus defined for Ethernet family PHY's registers read and write
Proprietary Header Allows custom field insertion anywhere inside the frame, staring from SFD till CRC field
Custom VLAN Allows customization of VLAN tags
Custom CRC length Allows configuration of number of bytes in a CRC field

Clause-37 Auto-negotiation

Auto-negotiation of 1000BASEX PHYs
Clause-73 Backplane Auto-negotiation Auto-negotiation for Ethernet backplane interfaces
Custom Message

Allows insertion of a message inside the Ethernet frame

Custom Preamble Custom preamble replaces the standard preamble of seven bytes, and Start Frame Delimiter with a random pattern header of n number of bytes, where n is configurable
Operational mode Active, Passive configuration
Supported frame types

802.3, MAGIC, JUMBO, PAUSE, PFC-PAUSE, VII, SNAP
Tagged frame - single tagged (Q-VLAN tag), double tagged (S-VLAN tag and Q-VLAN tag)

Speed of operation 10Mbps, 100Mbps, 1Gbps, 10Gbps, 20Gbps, 25 Gbps, 40Gbps, 100Gbps
Start-up protocol with link training support PMD link training as described in Clause 72 of IEEE 802.3
Upper Layer Packets and Stages Transport, network, Mpls, Snap and PTP

MacSec GCM-AES-256/128

Ethernet frames can be encrypted/decrypted with a user defined 256/128 bit Secure association key based on default cipher suites GCM-AES-256/128. Frames can be integrity or confidentiality protected

High Performance Mode for 20/25/40//50100G PHYs

High performance can be enabled for 20G, 25G, 40G, and 100G PHYs where serialization and deserialization logic has been moved to Verilog.

25Gbps Mac Support

Support the interface between MAC and PHY for 25Gbps speed.

802.1qav based Credit Based Shaper Algorithm Support

802.1qav based Credit Based Shaper Algorithm support for Time Sensitive Streams using QVLAN Enabled packets for all ENET Interfaces.

Supported Design-Under-Test Configurations

MAC PHY Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

Ethernet 25G/50G Simulation VIP Supports Energy Efficient Ethernet (EEE)

Specification Support

The 25G/50G specifications are developed and maintained by 25 Gigabit Ethernet Consortium and accessible at http://25gethernet.org/ as per Consortium rules.

Product Highlights

  • Supports broadest range of MAC interfaces
  • Supports Energy-Efficient Ethernet, Priority-Based Flow Control, and Ethernet Audio/ Video 
  • Optional TripleCheck product provides pre-silicon compliance tests for 40G/100G verification

Supported Interfaces

Interface
Supported speed and Duplex Kind
MII 10/100Mbps(Half/Full Duplex)
RMII 10/100Mbps(Half/Full Duplex)
SMII 10/100Mbps(Half/Full Duplex)
GMII 1Gbps(Half/Full Duplex)
TBI  1Gbps(Half/Full Duplex)
RTBI 1Gbps(Half/Full Duplex)
1000BASEKX 1Gbps(Half/Full Duplex)
RGMII 10/100Mbps and 1Gbps(Half/Full Duplex)
SGMII 10/100Mbps and 1Gbps(Half/Full Duplex)
QSGMII 10/100Mbps, 1Gbps 4 independent ports(Half/Full Duplex)
XGMII 10Gbps(Full Duplex only)
XSBI 10Gbps(Full Duplex only)
Xaui 10Gbps(Full Duplex only)
RXAUI 10Gbps(Full Duplex only)
TENGKX4 10Gbps(Full Duplex only)
TENGKR 10Gbps(Full Duplex only)
20GBASER 20Gbps (Full Duplex only)
40/100G CGMII 40/100Gbps (Full Duplex Only)
40GBASER/100GBASER 40/100Gbps (Full Duplex Only)
25G/50G XMII 25Gbps/50Gbps (Full Duplex Only)
25GBASER/50GBASER 25Gbps/50Gbps (Full Duplex Only)


Key Features

Feature
Description
Custom CRC User configurable CRC field
No Preamble Option to send an Ethernet Packet without Preamble, supported for limited interfaces
Priority pause based Flow Control (PFC)

Link level flow control for each Class of Service (CoS) as defined  by IEEE P802.1p

Pause Frame Based Flow Control

Flow control mechanism in which overwhelmed network element sends a Pause frame which halts the transmission for a specified period of time.

Forward Error Correction (FEC) FEC appends to the Ethernet frame additional data that is a result of set of non-binary arithmetic functions performed on the data of the Ethernet frame. This additional data (known as the FEC parity octets) is used to correct errors at the receiving end of the link that may occur when the data is transferred through the link.
Energy Efficient Ethernet (EEE)* EEE is a set of enhancements to the twisted-pair and backplane Ethernet family of computer networking standards that allow for less power consumption during periods of low data activity, per Standard IEEE 802.3az.
Management Data Input/Output(MDIO)* Serial bus defined for Ethernet family PHY's registers read and write. Supported for 10 Mbps, 100 Mbps, 1 Gbps, 10 Gbps, 20Gbps, 40Gbps and 100Gbps speeds.
Proprietary Header Allows custom field insertion anywhere inside the frame, staring from SFD till CRC field
Custom VLAN Allows customization of VLAN tags
Custom CRC Length Allows configuration of number of bytes in a CRC field
Clause-37 Auto-negotiation Auto-negotiation of 1000BASEX PHYs
Clause-73 Backplane Auto-negotiation Auto-negotiation for Ethernet backplane interfaces
Custom Message*

Allows insertion of a message inside the Ethernet frame

Custom Preamble* Custom preamble replaces the standard preamble of 7 bytes, and Start Frame Delimiter with a random pattern header of n number of bytes, where n is configurable
Operational Mode Active, Passive configuration
Supported Frame types

802.3, MAGIC, JUMBO, PAUSE, PFC-PAUSE, VII, SNAP
Tagged Frame - Single Tagged(Q-VLAN tag), Double tagged(S-VLAN tag and Q-VLAN tag)

 Speed of operation 10 Mbps, 100 Mbps, 1 Gbps, 10 Gbps, 20Gbps, 25Gbps, 40Gbps, 50Gbps and 100Gbps
Start-up protocol with link training support PMD link training as described in Clause 72 of IEEE 802.3
Upper Layer Packets and Stages Transport, network, Mpls, Snap and PTP
MacSec GCM-AES-256/128 Ethernet frames can be encrypted/decrypted with a user-defined 256/128-bit secure association key based on default cipher suites GCM-AES-256/128. Frames can be integrity or confidentiality protected.
High Performance Mode for 20/25/40/50/100G PHYs High performance can be enabled for 20G, 25G, 40G, 40G and 100G PHYs where serialization and deserialization logic has been moved to Verilog.
25Gbps and 50Gbps MAC/PHY Support Support the interface between MAC - PHY,  PHY sub-layers and TX-RX stations for 25Gbps/50Gbps speeds.
802.1qav based Credit Based Shaper Algorithm Support 802.1qav based Credit Based Shaper Algorithm support for Time Sensitive Streams using QVLAN Enabled packets for all ENETInterfaces.

Supported Design-Under-Test Configurations

MAC PHY Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

HDMI 1.4 Simulation VIP

Product Highlights

Specification Support

Our HDMI 1.4 Simulation VIP supports specification: HDMI Protocol v1.4b

Key Features

Feature Name
Description

3D – capability

Supports various 3D video frame formats

4K x 2K resolution

Supports 4Kx2K video frame formats

Consumer Electronics Control (CEC v1.3)

Supports six different types of CEC v1.3 device configurations

Custom Frame Format

Supports custom frame formats that allow users to configure frame formats that are DUT specific and not defined in the specification

Direct Data Channel (DDC)

Supports DDC channel, which is used by a HDMI source to determine the capabilities and characteristics of the sink by reading the E-EDID data structure

Expanded color spaces

Supports different types of extended color spaces exclusively defined within the HDMI specification

HDMI Packets

Supports all packet types defined in the HDMI Specification 1.4b

HDMI/DVI Mode

Supports both HDMI and DVI modes of operation. In HDMI mode of operation, the HDMI frame consists of video data, control data, and packets; while in DVI mode, HDMI frame consists of video data and control period only

High-bandwidth Digital Content Protection (HDCP 1.4)

Supports different types of HDCP encryption mode, supports Key Selection Vectors for transmitter and receiver. Supports transmission and reception of HDCP private keys. Supports Authentication bypass feature.

Serial and Symbol interfaces

Supports Serial and Symbol interface types

Source and sink

Supports verification of both Source (Tx) and Sink (Rx) device types

Vendor-specific info-frame packet

Supports user configurable, vendor-specific info-frame packet

 

Supported Design-Under-Test Configurations

Source Sink Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

 

HDMI 2.0 Simulation VIP The first VIP to support HDMI 2.0

Specification Support

Our HDMI 2.0 VIP supports features from HDMI Protocol version 2.0 R 16

Product Highlights

  • Industry's first HDMI 2.0 VIP

Key Features

Feature Name
Description

3D – Capability

Supports various 3D video frame formats

4K x 2K Resolution

Supports 4Kx2K video frame formats

3D - Guarantee interoperability for 25Hz formats

Supports 3D video formats for 25Hz frames

3D - Indication of independent view

Supports configuration of 3D Video extension registers in HDMI LLC Vendor Specific InfoFrame Packet

3D - Support Dual-view

Supports configuration of 3D Video extension registers in HDMI LLC Vendor Specific InfoFrame Packet

3D - Support OSD Disparity Indication

Supports configuration of 3D Video extension registers in HDMI LLC Vendor Specific InfoFrame Packet

21x9

Supports all 21:9 video formats defined by CEA-861-F specifications

Audio extensions

Supports 3D Audio and Multi-stream Audio

Consumer Electronics Control (CEC)

Supports 6 different types of CEC v1.3 device configurations.

Custom Frame Formats

Supports Custom Frame formats that allows user to configure frame formats that are DUT specific and not defined in the specification

Character Error Detection (CED) Supports the mechanism for detecting and reporting character errors
Deep Color Modes

Supports B24, B30, B36, B48 deep color modes.

Direct Data Channel (DDC)

Supports DDC channel which is used by an HDMI source to determine the capabilities and characteristics of the sink by reading the E-EDID data structure.

Expanded Color Spaces

Supports different types of extended color space exclusively defined within the HDMI specification

HDMI CTS 2.0 Compliance  Supports HDMI CTS 2.0 compliance checks

HDMI Packets

Supports all packet types defined in the HDMI Specification 2.0

HDMI/DVI Mode

HDMI VIP supports both HDMI and DVI mode of operation. In HDMI mode of operation, the HDMI frame consists of video data, control data, and packets; while in DVI mode, HDMI frame consists of video data and control period only

High-bandwidth Digital Content Protection 1.4 (HDCP 1.4)

Supports different types of HDCP encryption mode, supports Key Selection Vectors for transmitter and receiver. Supports transmission and reception of HDCP private keys. Supports Authentication bypass.

High-bandwidth Digital Content Protection 2.2 (HDCP 2.2) Supports Authentication and Key Exchange (with and without pairing). Supports locality check. Supports Session Key Exchange. SupportsTransmitter/Receiver State Machines. Supports Link Integrity Check. Supports Encryption (Cipher and Encryption Status Signaling)

Pixel Encoding 

Supports RGB, YCbCr 4:4:4 and YCbCr 4:2:2 pixel encodings

Scrambling for EMI/RFI reduction

Supports 340 Mcsc to 600 Mcsc TMDS Character Rate

Status and Control Data Channel (SCDC) Supports SCDC registers. Supports Read Request by slave

Source and Sink

Supports verification of both Source (Tx) and Sink (Rx) device types

Serial and Symbol interfaces

Supports Serial and Symbol interface types

YCbCr 4:2:0 Pixel Encoding Supports 4:2:0 based pixel encoding and frame packing/unpacking

Supported Design-Under-Test Configurations

Source Sink Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

User Feedback

"The HDMI 2.0 verification IP provided by Cadence enabled a small verification team to deliver reliable results within very tight schedule constraints. By reducing the effort required to develop a verification solution, our engineers were able to focus on other tasks crucial to project completion. As a result, we were able to create the type of high-quality and reliable design expected by our customers."

- Larry Porter, Verification Manager, Display Products Division, STMicroelectronics

 

I2C Simulation VIP

Product Highlights

Specification Support

The I2C VIP supports the I2C Protocol v1.0, v2.0, v2.1, v3.0, and v5.0 as defined in the I2C Protocol Specification.

Key Features

Feature Name
Description

Multiple agents

Supports both multi-mastering and any number of slaves

Arbitration Master arbitration is supported
Clock stretching Stretching of the SCL clock
7-bit/10-bit addressing Configurable option to use for slave addressing
General call Optional command support, configurable for each slave
Start byte Sending of optional start byte in transactions is available
Speed modes All speed modes are supported: Standard, Fast, Fast Plus and High Speed
Glitch handling Supports optional glitch handling
Slave response control Implements user control of slave response fields such as data, slave busy, slave sending NACK, etc.
Software reset Optional software reset command is supported
Device ID Optional command device ID is supported

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

JTAG Simulation VIP Provides JTAG and cJTAG support

Specification Support

This VIP supports specification versions: JTAG Protocol v1.c from 2001

Key Features

Feature Name
Description

Multiple slaves

Supports multiple slaves. Parallel/serial configuration is supported.

Instructions

Supports all standard defined instructions

Clamp

Optional instruction CLAMP is supported

High Z

Optional instruction HIGHZ is supported

Extest

Optional instruction EXTEST is supported

Extest pulse

Ooptional instruction EXTEST_PULSE is supported (from 1149.6 standard)

Extest train

Optional instruction EXTEST_TRAIN is supported (from 1149.6 standard)

Instruction length

Instruction length is configurable

Instruction codes

Instruction codes is configurable

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

LIN Simulation VIP

Specification Support

Our LIN Simulation VIP supports specification versions: 2.1, 2.0 and 1.3

Key Features

Feature Name
Description

Frame Library

Supports user frame library

Go-to-Sleep/Wake-up

Supports Go-to-Sleep and Wake-up feature

Master and Slave Configuration

Supports configuring a LIN cluster with one master agent and many slave agents

Node Capability File (NCF)

Supports NCF-like predefined configuration

Predefined Sequence

Supports various types of predefined sequences for functions like READ_BY_ID, ASSIGN_NAD, CONDITIONAL_CHANGE_NAD, DATA_DUMP, SAVE_CONFIGURATION, ASSIGN_FRAMR_ID_RANGE

Random Frames

Supports constrained random frames

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full stack Controller-only PHY-only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

MIPI CSI-2 Simulation VIP In production since 2008 on dozens of production designs

Specification Support

Our MIPI CSI-2 Simulation VIP supports the latest MIPI CSI2 and DPHY specifications.

Product Highlights

  • Industry's first CSI-2 VIP
  • Part of the broadest line of MIPI simulation VIP 
  • Features optional Accelerated VIP
  • Cadence has been a MIPI Alliance Contributing Member since 2007

Key Features

Feature Name
Description

Receiver and transmitter verification

Verifies both CSI-2 receiver and transmitter

Phy interfaces

Supports both PHY interfaces (DpDn and PPI)

Physical layer

Includes the MIPI D-PHY VIP for physical layer verification

Data lanes

Supports one to four data lanes

Interleaving

Supports virtual channel and data type interleaving

Ultra-Low Power mode (ULPM)

Supports Ultra-Low Power mode (ULPM)

Trigger

Supports trigger commands, including low-power data after trigger

Memory callbacks for DPHY event notifications

Supports D-PHY (DPDN+PPI) event notifications for scoreboarding

Error injection

Supports injection of errors in the CSI2 and DPHY layers

Data from a file (for e users only)

Supports driving frames from a user data file

Supported Design-Under-Test Configurations

Transmitter Receiver Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

MIPI CSI-3 Simulation VIP Includes the MIPI M-PHY and UniPro VIP

Specification Support

Our MIPI CSI-3 Simulation VIP supports specification versions: 1.0

Product Highlights

  • Industry's first CSI-3 VIP
  • Part of the broadest line of MIPI simulation VIP 
  • Cadence has been a MIPI Alliance Contributing Member since 2007

Key Features

Feature Name
Description

Spec 1.0 compliance

Complies with MIPI CSI3 specification version 1.0

CSI-3 host and camera
devices

Verifies CSI-3 host and camera
devices

Transmission of image and attribute packets

Supports transmission of image and attribute packets

Data transmission on
multiple virtual channels

Supports data transmission on
multiple virtual channels
PHY, PA, DLL, TL, and NL layers Supports PHY, PA, DLL, TL, and NL layers
Physical layer verification Includes the MIPI M-PHY VIP for PHY verification
Cport signaling IF Supports Cport Signaling IF

Supported Design-Under-Test Configurations

Transmitter Receiver Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

MIPI C-PHY Simulation VIP

Specification Support

The C-PHY VIP supports MIPI C-PHY specification Version 0.8

Product Highlights

  • First to market with C-PHY VIP support
  • Supports Low and High Speed transactions
  • Supports multi-lane configuration

Key Features

Feature Name
Description
CPHY symbol error injection Support an API to inject CPHY symbol errors (wrong symbol/missing symbol)
HS transactions Supports transmitting and receiving C-PHY High Speed transactions
Preamble and Sync Pattern and Post fields Supports all parts of HS transaction (Preamble -> Sync Pattern -> data -> Post pattern
Sync Symbol (Comma) Supports driving and detecting Sync Symbol during HS transaction
LP - HS transitions Supports transitions from LP to HS and vice versa
Number of lanes Supports 1 to 4 lanes

Supported Design-Under-Test Configurations

Transmitter Receiver
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

MIPI D-PHY Simulation VIP

Specification Support

Our MIPI D-PHY Simulation VIP supports the latest MIPI D-PHY specifications.

Product Highlights

  • Industry's first D-PHY VIP
  • Part of the broadest line of MIPI simulation VIP 
  • Cadence has been a MIPI Alliance Contributing Member since 2007
  • Supports one to four data lanes
  • Supports Ultra-Low Power mode (ULPM)

Key Features

Feature Name

Description

Phy interfaces

 

Supports both PHY interfaces (DpDn and PPI)

Physical layer

Includes the MIPI D-PHY VIP for physical layer verification

Data lanes

Supports one to four data lanes

Interleaving

Supports virtual channel and data type interleaving

Ultra-Low Power mode (ULPM)

Supports Ultra-Low Power mode (ULPM)

Trigger

Supports trigger commands, including low-power data after trigger

Memory callbacks for DPHY event notifications

Supports D-PHY (DPDN+PPI) event notifications for scoreboarding

Error injection

Supports injection of errors in the DPHY layers

Data from a file (for e users only)

Supports driving frames from a user data file

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

MIPI DigRF Simulation VIP The first VIP to support DigRF

Specification Support

Our MIPI DigRF Simulation VIP supports specification version 1.0

Product Highlights

  • Supports distribution and merging data over one to four lanes
  • Supports low-speed and high-speed transmission
  • Supports nesting and Automatic Repeat request (ARQ)

Feature Name

Description

Multiple lanes

Supports distribution and merging data over one to four lanes

Link speed

Supports low-speed and high-speed transmission

ARQ

Supports nesting and Automatic Repeat request (ARQ)

NACKs

Supports NACKs and retransmissions, including dummy frames

Supported Design-Under-Test Configurations

RFIC BBIc
Full Stack Controller Only PHY Only

 

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

MIPI DSI Simulation VIP In production since 2008 on dozens of production designs

Specification Support

This VIP supports specification versions:  1.1

Product Highlights

  • Industry's first DSI VIP
  • Part of the broadest line of MIPI simulation VIP 
  • Features optional Accelerated VIP
  • Cadence has been a MIPI Alliance Contributing Member since 2007

Key Features

Feature Name
Description

Receiver and transmitter verification

Verifies both DSI processor and peripheral

Physical layer (PHY)

Includes the MIPI D-PHY VIP for physical layer verification

PHY interfaces

Supports both PHY interfaces (DpDn and PPI)

Data lanes

Supports one to four data lanes
Power state Supports both high-speed and low-power data transmission

LP capabilities

Supports Ultra-Low Power mode (ULPM), triggers and LP data transmission

Transmission of multiple packets

Supports several merged packets in a single PHY transmission
Traffic modes

Supports sending and receiving of DSI packets and frames in command mode and all video modes

Accurate video mode timing Supports both generation and checks of accurate video mode timings
Control of payload data Enables the user to control the frame and packet payload

Supported Design-Under-Test Configurations

Transmitter Receiver Hub/Switch
Full Stack Controller Only PHY Only


Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

MIPI LLI Simulation VIP The world's first LLI VIP

Specification Support

The LLI VIP supports MIPI Low-Latency Interface specification version 2.0.

Product Highlights

  • First to market with LLI 2.0 VIP support
  • Supports extended data frames (PHIT36)
  • Supports automatic scrambling
  • Provides Interconnect Adaptation Layer (IAL) with AMBA® AXI

Key Features

Feature Name
Description

Spec 2.0 compliance

Complies with MIPI LLI specification version 2.0

PHY, PA, DLL, and transport layers

Supports PHY, PA, DLL, and transport layers

Automatic calculation and generation

Supports PA PHIT, CRC, and SEQ automatic calculation and generation

Extended data frames Supports PHIT36 (extended data frames)

Message and transaction frame

Supports DLL message and transaction frame

Flow control and mount/unmount

Supports DLL flow control and mount/unmount procedure

Protocol TCs Supports protocol TCs

TL_IC and TL_SVC packets

Supports all types of TL_IC and TL_SVC packets

Retransmission queue Supports retransmission queue

Physical layer (PHY) verification

Includes the MIPI M-PHY VIP for PHY verification

Interconnect adaptation layer (IAL)

Supports Interconnect Adaptation Layer (IAL) with AMBA® AXI

Scrambling Supports scrambling

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

MIPI M-PHY Simulation VIP First production M-PHY VIP

Specification Support

This VIP supports specification version: 3.0 and below

Product Highlights

  • Industry's first M-PHY VIP
  • Part of the broadest line of MIPI simulation VIP 
  • Cadence has been a MIPI Alliance Contributing Member since 2007

Key Features

Feature Name
Description
Specification compliance Compiles with MIPI M-PHY 3.0 specification

M-PHY Type 1 and Type 2

Supports Type 1 and Type 2

M-PHY interface

Supports serial interface (DpDn) and signaling interface (RMMI)

M-PHY modes

Supports BURST state, ACTIVATED SAVE states (SLEEP and STALL) and hibernate (“HIBERN8”) state
M-PHY transmission modes

Supports multiple transmission modes with different bit-signaling and clocking schemes

Supports multiple transmission speed ranges (PWM G1-G7, all Hs-GEARs) and rates per BURST mode

Multi-lane

Supports distribution and merging data over one to four lanes. Also supports a different number of lanes per sub-link (direction)

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

User Feedback

"Mobile device users demand ever-increasing power-efficiency, and the MIPI Alliance chip-to-chip interfaces are an essential low-power technology for smartphone and tablet developers. As an early contributing member of the MIPI Alliance, Cadence has helped speed the adoption of mobile specifications, now including the M-PHY-based M-PCIe."
– Joel Huloux, Chairman of the Board, MIPI Alliance

MIPI SLIMbus Simulation VIP Used on dozens of MIPI verification projects

Specification Support

This VIP supports the latest SLIMbus specification

Product Highlights

  • Industry's first SLIMbus VIP
  • Part of the broadest line of MIPI simulation VIP 
  • Cadence has been a MIPI Alliance Contributing Member since 2007

Key Features

Feature Name
Description
Transmits and receives all message types Supports all protocol messages
Transport protocols Supports SLIMbus transport protocols (Isochronous, Pushed, Pulled, Async Simplex, Async Half-Duplex, Extended Asyncs)
Bus reconfiguration and bus synchronization Supports component boot-up sequence and recovery of sync loss
Root frequency and clock gear Provides ability to change root freq and clock gear
Information/value elements Supports information/value element messages
Full reset flow Supports all kinds of protocol resets
Active framer Supports all roles of Active Framer (Framing Channel and clocks)
Active framer handover Support the active framer handover flow
Clock pause Supports Clock Pause flows

Supported Design-Under-Test Configurations

Active Manager Generic Device Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

MIPI Soundwire Simulation VIP

Specification

The SoundWire VIP supports MIPI SoundWire specification version 0.7.8.

Product Highlights

  • First to market with SoundWire VIP support
  • Enables emulation with up to 11 slaves, with 1 to 14 data ports per slave
  • Supports Initialization sequence and enumeration process
  • Supports multi-lane configuration

Key Features

Feature Name
Description
Synchronization Sync slave with master SoundWire frame
Enumeration Master assigns Dev_num for each newly attached slave
Data payload Traffic

Slave and Master devices can send data payload traffic

Bank switching

Frame size and DP channels can be switched during activity

Resets

Ability to perform all kinds of resets on the fly
Error Scenarios Master and Slave can generate error scenarios
Interrupts Slave VIP replies automatically when interrupt needs to be generated based on configuration
Dynamic slave devices Dynamic addition and removal of Slave devices
Multicast and broadcast slave accesses Master can access slave registers through broadcast and multicast
Test data modes Support of static and PRBS data payload sending
Slave command responses Slave VIP automatically replies with appropriate command responses
Command ownership Monitor can take command ownership from Master

Supported Design-Under-Test Configurations

Master Slave Monitor
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

MIPI UniPro Simulation VIP Industry's first UniPro VIP

Specification Support

This VIP supports specification versions: 1.41, 1.6

Product Highlights

  • Industry's first UniPro VIP
  • Part of the broadest line of MIPI simulation VIP 
  • Cadence has been a MIPI Alliance Contributing Member since 2007

Key Features

Feature Name
Description

Up-to-date specification

Supports both MIPI UniPro 1.6 and 1.41 specifications

Serial and RMMI interfaces Supports serial and RMMI interfaces (downstream)
CPort signal interface Supports CPort signal interface (upstream)
All layers supported Supports PHY adapter, data link, network, and transport layers
Built-in sequences PA link start up, (re-)initialization, configuration, and hibernate enter/exit sequences
Data link layer Supports DLL initialization, TC0 and TC1, flow control, and acknowledgement mechanisms

Transport layer

Supports TL connection management and addressing, segmentation and reassembly,
end-to-end flow control, and multi-CPort arbitration 
Lane capabilities Supports up to four lanes: PWM G1-G7, HS G1-G3 on each direction, and A/B HS rate series
Connectivity capabilities Supports testing of 1.41 to 1.6 connection compatibility

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

Mobile High-Definition Link (MHL) Simulation VIP

Specification Support

Cadence MHL VIP is compliant with MHL specification version 3.0. The specification is developed by the MHL Consortium http://www.mhlconsortium.org/  and is available only for the licensed users.

Key Features

Feature Name
Description

Pixel Encoding 

Supports RGB, YCbCr 4:4:4 and YCbCr 4:2:2 MHL specification

Video Data Encoding Supports 24bits and 16bits per pixel mode
3D – Capability   Supports various 3D video frame formats
Custom Frame Format Supports Custom Frame formats that allows user to configure frame formats that are DUT specific and not defined in the specification
MHL Packets Supports all packet types defined in the MHL Specification 3.0
Serial and Symbol interfaces Supports Serial and Symbol interface types
Source and Sink Supports verification of both Source (Tx) and Sink (Rx) device types
Vendor Specific Info-Frame Packet Supports user configurable, vendor specific Info-Frame Packet

Supported Design-Under-Test Configurations

Source Sink
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

Mobile PCI Express Simulation VIP First VIP to support Mobile PCI Express

Specification Support

The base spec for PCIe 3.0 and ECN for M-PCIe can be downloaded only by members of the PCI-SIG website: http://www.pcisig.com/home.

Product Highlights

  • First VIP to support the Mobile PCI Express specification
  • Part of a complete PCI Express solution including:
    • PCI Express Gen3
    • PCI Express Gen2
    • NVM Express
    • Mobile PCI Express
    • SR-IOV
    • MR-IOV
  • Supports the latest specification ECNs
  • Optional TripleCheck product provides a complete pre-silicon compliance testing solution
  • Supports distribution and merging data over one to four lanes
  • Supports RMMI and serial physical interfaces
  • Supports RRAP mode and LRC
  • L1/L2 (including support for local reset)
  • Supports ACTIVATED SAVE states (SLEEP and STALL) and HIBERN8

 

Feature Name
Description
HS-BURST

Supports all High Speed burst gears (HS-G1/HS-G2/HS-G3) and date rate series(A/B)

LS-MODE Supports Low Speed burst mode called Pulse Width modulation(PWM-G1)
Bandwidth reconfiguration Supports the bandwidth reconfiguration via Recovery states
Multi-LANE capability Support x1, x2, x4, x8, x12, x16, x32 lanes
RRAP Supports remote register access protocol

Type-I compliant

Compliant with Type-I M-PORTs from the MIPI M-PHY specifications
Dynamic link change TX/RX link width can be changed via Recovery.Reconfig state
Asymmetric lane support TX and RX link width can be chosen to be different
STALL in L0 TX-Lanes can be directed to enter STALL in L0 state

Supported Design-Under-Test Configurations

Root Complex End Point Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

User Feedback

"M-PCIe helps boost mobile device performance by delivering best-in-class, highly scalable I/O functionality, enabling the migration of business apps to smartphones and tablets as they take on the role of primary computing devices. We are delighted that Cadence is enabling SoC developers to rapidly adopt M-PCIe by delivering IP and VIP products supporting this standard."
- Al Yanes, Chairman and President, PCI-SIG

NVM Express Simulation VIP World's first NVM Express VIP

Specification Support

This VIP supports specification versions: 1.0c, 1.1

Product Highlights

  • First VIP to support NVM Express
  • Part of a complete PCI Express solution including:
    • PCI Express Gen3
    • PCI Express Gen2
    • NVM Express
    • Mobile PCI Express
    • SR-IOV
    • MR-IOV
  • Supports the latest specification ECNs

Key Features

Feature Name
Description

Registers

Supports all registers including system bus (PCI Express) registers and controller registers

Command set Full support of the admin command and NVM command sets specified in NVMe specification version 1.0c
PRP entry and list

Supports physical region page (PRP) entry that points to a physical memory page
Supports PRP list, which is a set of PRP entries

Metadata Supports metadata per logical block
Namespace Provides support for namespace management
Queues Provides full support for admin completion/submission queues and I/O completion/submission queues
Logical black address (LBA) Supports logical block address (LBA)
Firmware update process Supports firmware update process
Interrupt

Supports four different interrupt reporting modes: pin-based interrupt, single message MSI, multiple message MSI, and MSI-X

Power management

Enables host to manage NVM subsystem power statically or dynamically.
Supports up to 32 power states

Shutdown Supports either a normal shutdown or an abrupt shutdown
Command arbitration Supports different command arbitration mechanisms: the round-robin arbitration, weighted round robin with urgent priority class arbitration, and vendor-specific arbitration

Supported Design-Under-Test Configurations

Host Controller Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

OCP 2.2 Simulation VIP Used on over 100 design projects

Specification Support

Our OCP VIP supports the OCP protocol v2.2, which is incremental to OCP versions 2.1 and 2.2.

Product Highlights

 

Key Features

Feature Name
Description
Blocking and non-blocking flow control options Supports both the blocking and non-blocking flow control options for the requests
Clock enable Supports the enable signal for clock
Connect/disconnect feature Supports Connect-Disconnect feature for both master and slave
Enhanced semantics for the write response enable Ensures that the WriteNonPost (WRNP) and WriteConditional (WRC) commands always have responses regardless of whether write response enable has been set in the interface configuration, as defined in the OCP 2.2 specification
Generating and driving bus traffic as an OCP master Emulates the full behavior of an unlimited number of OCP masters capable of generating all types of OCP transfers, according to OCP 2.2 specification
Multithreading and tagging Supports multiple thread IDs and multiple tag IDs
Out-of-order response Supports out-of-order responses
Request interleaving Supports request interleaving. The interleaving depth is determined from the signal, MAtomicLength
Responding to bus traffic as an OCP slave Emulates the full behavior of an unlimited number of OCP slaves that respond to traffic over a bus, and generates all types of responses to a DUT master, according to OCP 2.2 specification
Synchronous and asynchronous reset Supports both synchronous and asynchronous reset. Also supports reset on-the-fly

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

OCP 3.0 Simulation VIP First VIP to support OCP 3.0

Specification Support

This OCP VIP supports the OCP-IP Protocol version 3.0, which is incremental to OCP-IP Protocol version 2.2.

Product Highlights

 

Key Features

Feature Name
Description
Blocking and non-blocking flow control options Supports both the blocking and non-blocking flow control options for the requests
Cache coherence extension Partially supports the cache coherence feature. It supports both the main port and legacy port functionality. It supports only self-intervention as part of the intervention port functionality.
Clock enable Supports the enable signal for clock
Connect/disconnect feature Supports Connect-Disconnect feature for both master and slave
Enhanced semantics for the write response enable Ensures that the WriteNonPost (WRNP)/WriteConditional (WRC) commands always have responses regardless of whether write response enable has been set in the interface configuration, as defined in the OCP 2.2 specification
Generating and driving bus traffic as an OCP master Emulates the full behavior of an unlimited number of OCP masters capable of generating all types of OCP transfers, according to OCP 2.2 specification
Multi-threading and tagging Supports multiple thread IDs and multiple tag IDs
Out-of-order response Supports out-of-order responses
Request interleaving Supports request interleaving. The interleaving depth is determined from the signal, MAtomicLength.
Responding to bus traffic as an OCP slave Emulates the full behavior of an unlimited number of OCP slaves that respond to traffic over a bus and generates all types of responses to a DUT master, according to OCP 2.2 specification
Synchronous and asynchronous reset Supports both synchronous and asynchronous reset. It also supports reset on-the-fly.

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

PCI Simulation VIP

Specification Support

The PCI VIP supports the PCI Protocol versions 1.0, 2.0, 2.1, 2.2 and 2.3

Key Features

Feature Name
Description

Bus data width

Supports both 32- and 64-bit bus data widths 

Arbitration Supports master arbitration 
Multiple agents Supports multi-mastering and configurable number of target agents
Interrupt pins Supports configurable number of optional interrupt pins 
Power management Supports power management registers 
Lock Supports lock feature 
Multi-function device Supports configurable number of functions per device
Burst types Supports both linear and cache line wrap modes for both read and write
64-bit addressing Supports optional 64-bit addressing
Transaction termination Supports all transaction termination types: Completion, Master-Abort, Timeout, Retry, Disconnect with/without data, and Target-Abort

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only


Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

PCI Express Gen2 Simulation VIP The most mature PCIe VIP, used by more than 100 customers

Specification Support

This VIP is fully compliant with the 2.1 revision of the PCI Express specification.

Product Highlights

  • Part of a complete PCI Express solution including:
    • PCI Express Gen3
    • PCI Express Gen2
    • NVM Express
    • Mobile PCI Express
    • SR-IOV
    • MR-IOV
  • Supports the latest specification ECNs
  • OptionalTripleCheck product provides a complete pre-silicon compliance testing solution
  • Features optional Accelerated VIP

Key Features

Feature Name
Description
LTSSM modeling and checking Complete link training status state machine (LTSSM) modeling, including all configuration, power-saving, and recovery states
Speed negotiation Full control of the link speed, up and down changes
Up-configuration Full support for up and down configuration (link size)
Skew Adding skew between lanes
Clock recovery Recover clock from bitstream or use reference clock
Clock jittering Add jitter to the clock
Ack\Nak Full control of the Ack\Nak protocol and timers, predefined sequence number, link CRC (LCRC), and duplicate TL error injections
Flow control credits Full control of Flow Control Credits (FCCs), including initial allocation of FCCs and the frequency of on-the-fly FCC updates
All interfaces Serial, 8-bit, 10-bit, PIPE 3.0, PIPE 4.0, PIE8
Support for all sidebands WAKE#, CLKREQ#, PERST#
Support for major devices End Point, Legacy End Point, Root Complex, Bridge, Switch, PHY-DUT
Complete modeling of four address spaces Memory, I\O, Configuration, MSI\MSI-X
Virtual channels Automatic, user-defined flow control initialization per virtual channel (VC)
Function level reset Full compliance

Supported Design-Under-Test Configurations

Root Complex End Point Switch/Bridge
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

User Feedback

"When faced with the important decision as to which IP vendor has the most reputable and silicon-proven PCI Express IP, Denali (now Cadence) was the preferred vendor that met our critical high throughput and feature requirements. We rely on Cadence's high-quality, interoperable design and verification IP solutions, and excellent customer support to meet the PCIe 2.0 and IOV specifications, our product development timeframes, and achieve a competitive advantage. "
- Jim Finnegan, Sr. Vice President of Silicon Engineering, Netronome

PCI Express Gen3 Simulation VIP The most complete and capable PCIe 3.0 VIP

Specification Support

The VIP is fully compliant with the 3.0 revision of the PCI Express spec

Product Highlights

  • Part of a complete PCI Express solution including:
    • PCI Express Gen3
    • PCI Express Gen2
    • NVM Express
    • Mobile PCI Express
    • SR-IOV
    • MR-IOV
  • Supports the latest specification ECNs
  • OptionalTripleCheck product provides a complete pre-silicon compliance testing solution
  • Features optional Accelerated VIP

Key Features

Feature Name
Description

Equalization Procedure

Perform and control all equalization aspects

DC Balance Full support for the new TS symbols
Framing Tokens Error injection, checking, and coverage
Clock Compensation New Skip OS full support
PMUX Protocol multiplexing ECN
OBFF Optimized buffer flush\fill
ASPM Optionality ASPM optionality ECN
L1 PM Sub-States L1 sub states ECN
DPC Downstream port containment ECN
LN Lightweight notification ECN
M-PCIE PCIe over M-PHY ECN
PASID Process address space ID ECN
PTM Precision time measurement ECN

Supported Design-Under-Test Configurations

Root Complex End Point Switch/Bridge
Full stack Controller-only PHY-only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

User Feedback

"Wipro has been consistently enabling semiconductor companies to reduce verification time and increase coverage parameters through its next-generation frameworks and market-proven end-to-end verification services. Our partnership with Cadence has played an instrumental role in fulfilling the IP verification needs of our customers. We chose PCIe Gen3 VIP along with TripleCheck by Cadence to achieve a comprehensive solution that gives us the fastest path to IP verification closure."
- A. Vasudevan, VP Semiconductor and Systems, Wipro

"We’ve determined that 90% of the risk is in the chip’s interfaces. If we design the interfaces incorrectly, it doesn’t matter if we get the rest of the chip right. This is especially true with PCI Express since it’s such a complex protocol. The bottom line for us is that the choice we made to go with proven IP that’s easy to get up and running is really just good, solid common sense. "
- Jim O’Connor, Vice President of Engineering, iVivity

PCI Express Gen4 Simulation VIP First VIP to provide support for PCIe Gen4

Specification Support

This VIP is compliant with draft 0.3 of PCI Express spec 4.0.

Product Highlights

  • Provide support for Gen4 equalization testing
  • Supports x1, x2, x4, x8, x12, x16, and x32 lanes 
  • Supports the latest engineering change notices (ECNs)
  • Speed negotiation and operation at 16GT/s

Part of a complete PCI Express solution including:

  • PCI Express Gen3
  • PCI Express Gen2
  • NVM Express
  • Mobile PCI Express
  • SR-IOV
  • MR-IOV
  • Supports the latest specification ECNs

Key Features

Feature Name
Description
Speed Negotiation at 16GT/s Full control of the link speed, up and down changes

Equalization procedure at 16GT/s

Perform and control all equalization aspects

Inferring EI for 16GT/s

Detecting inferred electrical idle
LTSSM modeling and checking Complete link training status state machine (LTSSM) modeling, including all Configuration, Power Saving, and Recovery states
Up-configuration Full support for up and down configuration (link size)
Skew Adding skew between lanes
Clock Recovery Recover clock from bit stream or use reference clock
Clock jittering Add jitter to the clock
Ack\Nak Full control of the Ack\Nak protocol and timers, Predefined sequence number, link CRC (LCRC), and duplicate TL errorinjections
Flow Control Credits Full control of Flow Control Credits (FCCs), including initial allocation of FCCs and the frequency of on-the-fly FCC updates.
All interfaces Serial, 8bit, 10bit, PIPE 3.0, PIPE 4.0, PIE8
Support for all sidebands WAKE#, CLKREQ#, PERST#
Support for major devices End Point, Legacy End Point, Root complex, Bridge, Switch, PHY-DUT
Complete modeling of 4 address spaces Memory, I\O, Configuration, MSI\MSI-X
Virtual Channels Automatic, user-defined flow control initialization per virtual channel (VC)
Function Level Reset Full compliance.
DC Balance Full support for the new TS symbols
Framing Tokens Error injection, checking, and coverage
Clock Compensation New Skip OS full support
PMUX Protocol multiplexing ECN (Engineering Change Notice)
OBFF Optimized buffer flush\fill
ASPM optionality ASPM optionality ECN
L1 PM sub-states L1 sub states ECN
DPC Downstream Port Containment ECN
LN Lightweight Notification ECN
M-PCIE PCIe over M-PHY ECN
PASID Process Address Space ID ECN
PTM Precision Time Measurement ECN

Supported Design-Under-Test Configurations

Root Complex End Point Switch/Bridge
Full stack Controller-only PHY-only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

PCIe SR-IOV Simulation VIP

Specification Support

This VIP supports specification versions: Single Root I/O Virtualization and Sharing Specification Revision 1.1

Product Highlights

  • Part of a complete PCI Express solution including:
    • PCI Express Gen3
    • PCI Express Gen2
    • NVM Express
    • Mobile PCI Express
    • SR-IOV
    • MR-IOV
  • Supports the latest specification ECNs

Key Features

Feature Name
Description

Generate traffic to target all functionality defined by the spec

 Supported

EROM Supports access to PF EROM
Function level reset Per VF FLR
VF migration Supported
ARI Alternative routine ID
VF sharing header log files VF can use the same header log files

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

PCIe MR-IOV Simulation VIP

Specification Support

This VIP supports the Multi-Root I/O Virtualization and Sharing Specification Revision 1.0

Product Highlights

  • Industry's first MR-IOV VIP
  • Part of a complete PCI Express solution including:
    • PCI Express Gen3
    • PCI Express Gen2
    • NVM Express
    • Mobile PCI Express
    • SR-IOV
    • MR-IOV
  • Supports the latest specification ECNs

Key Features

Feature Name
Description

Virtual link

VL=0

TLP prefix tagging generation Addition of the MR prefix to TLPs
Per-VH reset  Supported
Message processing INTx\PM
Base error detection and logging  Supported
MRA switch hot plug  Supported
Congestion management  Supported

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

PLB 6 Simulation VIP The leading VIP for PLB designs

Specification Support

The specifications for PLB4/6 are IBM confidential. 

Key Features

Feature Name
Description

Protocol

Supports command, read data, and write data buses

Interface Supports master/slave/snooper pin, snoopable/non-snoopable commands
Address ordering Supports address overlapping read/write
Cache coherency Supports cache coherency for snoopers
Data transfer Supports bytes, half-word, word, or line/burst transfer

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only


Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

User Feedback

"As the demand increases for interoperable and platform-independent Power Architecture solutions, Denali (now Cadence) has continually provided invaluable expertise in the toolkit development for the latest PLB specifications. IBM's collaboration with Cadence gives designers the ability to quickly implement customized Power Architecture based applications in world-leading semiconductor technologies."
- Michael Paczan, Chairman, Technical Committee, Power.org

 

SAS 6G Simulation VIP Used to verify leading hard disk controllers

Specification Support

This VIP supports specification versions: SAS (Serial Attached SCSI) Specification SPL-2

Key Features

Feature Name
Description
Address frame arbitration Supports arbitration between multiple OPEN address frames
Expander support Supports basic expander functionality
Frame Bursting Feature Supports frame bursting for READ/WRITE commands
INITIATOR and TARGET Supports verification of both INITIATOR and TARGET SAS device types
Interlocked and Non-interlocked transmission Supports frame transmission as per interlocked and non-interlocked frame type
Link Connection Control Supports all LINK layer state machines for connection control, transmitter, receiver
Link flow control Supports RRDY, CREDIT_BLOCKED etc primitives which are used for flow control
Link reset sequence Supports PHY Reset Sequence, Hard Reset Sequence, and Link Identification sequence
Operating modes Supports G1/G2/G3 speeds (1.5/3/6Gbps)
PHY reset sequence Supports OOB sequence, Speed Negotiation Sequence
PHY and LINK timers Supports all PHY/LINK layer timers
PHY training sequence

Supports PHY training sequence at 6Gbps

Rate matching feature Supports link rate matching feature at 1.5/3/6Gbps
SAS frame types Supports all frame types for INITIATOR and TARGET: SSP_COMD, SSP_DATA, SSP_TASK, SSP_XFER, SSP_RESP

SPL-3 Persistent-Connection

Support for SPL-3 Persistent-Connection feature

Transport layer protocols Supports SSP and SMP transport layer protocols
Wide-port support Supports wide-port of x2 and x4 (2/4 PHYs) configuration

Supported Design-Under-Test Configurations

Initiator Target Expander
Full stack Controller-only PHY-only

 

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

SAS 12G Simulation VIP Production proven verification capability

Specification Support

This VIP supports SAS (Serial Attached SCSI) Specification revision 11-036r9

Key Features

Feature Name
Description
Address frame arbitration Supports arbitration between multiple OPEN address frames
BMC Encoding/Decoding Supports BMC encoding/decoding feature of PHY
Error TTIUs and Error Response TTIUs Supports transmission and reception of Error TTIUs and Error Response TTIUs
Frame Bursting Feature Supports Frame bursting for READ/WRITE commands
INITIATOR and TARGET Supports verification of both INITIATOR and TARGET SAS device types
Interlocked and non-interlocked transmission Supports frame transmission as per interlocked and non-interlocked frame type
Link connection control Supports all LINK layer state machines for connection control, transmitter, receiver
Link flow control Supports RRDY, CREDIT_BLOCKED etc primitives which are used for flow control
Link reset sequence Supports PHY reset sequence, hard reset sequence, and link identification sequence
Operating modes Supports G1/G2/G3/G4 speeds (1.5/3/6/12Gbps)
PHY and LINK timers Supports all PHY/LINK layer timers
PHY reset sequence Supports OOB sequence, speed negotiation sequence
PHY training sequence

Supports PHY training sequence at 6Gbps

PHY transmitter/receiver training sequence Supports PHY transmitter/receiver training sequence at 12Gbps
Rate matching feature Supports link rate matching feature at 1.5/3/6/12Gbps
SAS frame types Supports all frame types for INITIATOR and TARGET: SSP_COMD, SSP_DATA, SSP_TASK, SSP_XFER, SSP_RESP

SPL-3 Persistent-Connection

Support for SPL-3 Persistent-Connection feature

Transport layer protocols Supports SSP and SMP transport layer protocols

Supported Design-Under-Test Configurations

Initiator Target Expander
Full Stack Controller Only PHY Only


Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

SATA 6G Simulation VIP Trusted by dozens of customers

Specification Support

Cadence Verification IP for SATA provides support for SATA Specification version 3.1

Product Highlights

 

Key Features

Feature Name
Description
ACS -3 Supports many feature sets and commands from ACS commands 
ASR Asynchronous Signal Recovery
ATAPI commands ATA packet interface support
Embedded port multiplier

Device behaves as if it has multiple memory subsystems to behave as port multiplier
Coherent read and write to different ports
Different feature configurations for each port (Eg. Port 0 ATA, Port 1 ATAPI)

Finite state machine (FSM) All finite state machines and state transition checks
Initialization Clock recovery and speed negotiation, OOB signaling with different OOB data, signature FIS, error injection and speed up of bypass initialization

Interface

Supports serial 1-bit as well parallel 10/20/40-bit interface

Interface power states Partial, slumber, device sleep
Memory subsystem System, buffer, and log memory
NCQ Native Command Queueing
FSM All the Finite state machines and state transition checks
Protocol checks Does protocol checks at each layer, such as physical, link, transport, and command
PIO and DMA engine Multiple PRD table implementation
Protocol checks Does protocol checks at each layer, such as physical, link, transport and command
Controllable protocol checkers and passive monitors 
Send/Receive FPDMA Queued Commands Send and Receive FPDMA Queued Commands
DMATp primitive Terminate a DMA data transmission

Supported Design-Under-Test Configurations

Host Device Port Multiplier
Full Stack Controller Only PHY Only


Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

SRIO Simulation VIP Includes Rapid IO support

Specification Support

This VIP supports specification versions: 1.3, 2.0, and 2.1

Key Features

Feature Name
Description

IO Logical

Input/Output packet formats are supported

Message Passing

Message passing architecture and packet formats are supported

Globally shared Memory

Globally shared distributed memory model architecture and packet formats are supported

Flow Control

Flow Control Logical Layer management based on source, destination and physical channel is supported

Data Streaming

Data Streaming Logical specification is supported

Multi-Lane

1x, 2x, 4x, 8x and 16x Lanes are supported

IDLE2

Both IDLE1 and IDLE2 sequences and therefore Short and Long Control Symbols are supported

VC support

Multiple virtual channels on PHY are supported

CT

Both reliable and continuous traffic (RT and CT) are supported

Phy Flow Control

Both receiver-ended and transmitter-controlled flow control on Physical Layer are supported

EndPoint Device

EndPoint Device features are supported

Transport Large Device

Both small and large device IDs are supported

Supported Design-Under-Test Configurations

Host Device Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

SRIO 3.0 Simulation VIP

Specification Support

The SRIO 3.0 VIP supports SRIO Protocol versions 3.0 as defined in the SRIO Protocol Specification. 

Key Features

Feature Name
Description

IO Logical

Input/Output packet formats are supported

Message Passing

Message passing architecture and packet formats are supported

Globally shared Memory

Globally shared distributed memory model architecture and packet formats are supported

Flow Control

Flow Control Logical Layer management based on source, destination and physical channel is supported

Data Streaming

Data Streaming Logical specification is supported

Multi-Lane

1x, 2x, 4x, 8x and 16x Lanes are supported

IDLE2

Both IDLE1 and IDLE2 sequences and therefore Short and Long Control Symbols are supported

VC support

Multiple virtual channels on PHY are supported

CT

Both reliable and continuous traffic (RT and CT) are supported

Phy Flow Control

Both receiver-ended and transmitter-controlled flow control on Physical Layer are supported

EndPoint Device

EndPoint Device features are supported

Transport Large Device

Both small and large device IDs are supported

SRIO 3.0 Features

64b/67b Encoding

Support for 64b/67b encoding: codewords, ordered sequences, and IDLE3

Lane Speed

Support for 10.3125 Gbaud lane speed

ackID Size

Increase ackID size for IDLE3 to 12 bits

Large Packets

Support for large packets, Dev32

Gbaud Links

Specific link initialization state machines to support initialization of 10.3125 Gbaud links

Gbaud Links

Asymmetric operation of 10.3125 Gbaud links

Multiple Packets

Allowed Packet Accepted control symbols to acknowledge multiple packets

Error Recovery

Input/output error recovery protocol updated in order to enable faster recovery

Per-port Register Block Format

New per-port register block format, with new/modified registers

Time Synchronization

Added time synchronization support

Supported Design-Under-Test Configurations

Host Device Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

SSIC Simulation VIP The first SuperSpeed Inter-Chip VIP

Specification Support

The base specifications for the SSIC and USB 3.0 protocols are available here: http://www.usb.org/developers/docs

Product Highlights

  • Industry's first SSIC VIP

Key Features

Feature Name
Description
HS-BURST

Supports all high-speed burst gears (HS-G1/HS-G2/HS-G3) and date rate series (A/B)

LS-MODE Supports low-speed burst mode called pulse-width modulation (PWM-G1)
LINE-RESET Supports LINE-RESET mechanism for warm reset
Multi-LANE capability Supports x1, x2, x4 lanes
RRAP Supports remote register access protocol
Type-I compliant Compliant with Type-I M-PORTs from the MIPI M-PHY specifications

Supported Design-Under-Test Configurations

Host Device Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

UART Simulation VIP

Specification Support

The UART VIP supports the standard UART 16550 Specification

Product Highlights

  • Compatible with industry-standard UART 16550 
  • Full-duplex asynchronous communications
  • Auto baud rate detection
  • Programmable data word length (7, 8 or 9 bits)
  • Configurable stop bits (1 or 2 stop bits)
  • Three error detection flags
  • Four interrupt sources with flags
  • Fully prioritized interrupt handling
  • Support for up to 128-byte transmit and receive FIFOs

Protocol Highlights

Feature Name
Description
Full-duplex Support for full-duplex asynchronous communications 
Baud Rate
  • Baud rate generation subsystem
  • Auto baud rate generation
Data Word Length Programmable data word length (7, 8 or 9 bits)
Stop Bits/Character  Configurable stop bits (1 or 2 stop bits)

Error detection flags

  • Overrun error
  • Frame error
  • Parity error

Fully Prioritized Interrupt sources

  • RX data available
  • TX holding register empty
  • RX line status interrupt
  • Modem status interrupt

TX/RX FIFOs

Support for up to 128-byte Transmit and Receive FIFOs

Supported Design-Under-Test Configurations

Transmitter Receiver Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

 

USB 2.0 Simulation VIP Part of a complete USB verification solution

Specification Support

This VIP supports specification versions: USB 2.0 and OTG 2.0

Product Highlights

  • Includes OTG support
  • Optional SuperSpeed Inter-Chip (SSIC) simulation VIP 
  • Optional PureSuite product with extensive pre-silicon compliance tests

Key Features

Feature Name
Description
All transaction types

Supports all types of transfers: bulk, control, interrupt, and isochronous and split transactions

Backward compatibility Backwards-compatible with USB 1.1 specifications
Enumeration

Provides a complete USB protocol hierarchy enumeration process for host, device, and hub models

Operational speed Operates at high, full, or low speed
OTG support Supports OTG 1.3 and OTG 2.0 revisions with both A-device and B-device configurations
OTG protocols Supports SRP (session request protocol), ADP (attach detection protocol), and HNP (host negotiation protocol)
Reset signaling

Supports reset and high-speed chirp handshake

Suspend/Resume Supports suspend, resume, remote wake-up, and low-power management (LPM)
Transaction and packet checks Checks for all transaction and packet rules including inter-packet gap and propagation delays
UTMI+ levels Supports all UTMI+ levels (1, 2, 3)

Supported Design-Under-Test Configurations

Host Device Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

User Feedback

"The Cadence SuperSpeed USB VIP has helped PLDA to be one of the first IP vendors to reach the market, while ensuring it is among the highest quality products available. Using Cadence VIP has enabled PLDA to achieve significantly greater functional coverage results."
- Stephane Hauradou, Chief Technology Officer, PLDA

USB 3.0 Simulation VIP Incudes support for OTG 3.0

Specification Support

The base specifications for the USB 3.0 protocol are available here:http://www.usb.org/developers/docs

Product Highlights

  • Includes OTG support
  • Provides optional SuperSpeed Inter-Chip (SSIC) simulation VIP 
  • Features optional PureSuite product with extensive pre-silicon compliance tests

Key Features

Feature Name
Description
Backward compatibility

Supports backward compatibility with USB 2.0, in high- and full-speed modes

Bulk stream Supports USB 3.0 bulk streaming protocol
Compliance state Supports all compliance patterns as part of compliance LTSSM state
Enumeration

Provides a complete USB protocol hierarchy enumeration process for host and device models

Link training Supports USB 3.0 link training with all LTSSM state transitions and covers all arcs
LMP Supports link management packet flow
Loopback and BERT Supports PHY loop-back state with bit error rate test
Low-power management Supports all low-power entry/exit sequences to U1, U2, and U3 states
OTG support Supports OTG 3.0 support and role swapping protocol (RSP)
Protocol checks Does protocol checks at each layer, such as physical, link, protocol, and framework
Smart isochronous Supports the USB 3.0 smart isochronous transfers
SSC Supports spread spectrum clocking

Supported Design-Under-Test Configurations

Host Device Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

User Feedback

"Cadence USB 3.0 Verification IP has enabled us to thoroughly verify that our designs comply with the USB 3.0 specification, and this new SSIC product demonstrates the company’s commitment to supporting engineers working with this key protocol. By supporting all popular verification methodologies and simulators, the Cadence VIP has enabled GUC to support our diverse customer base with high-quality SoC and IP verification coverage."
– James Cheng, Senior Vice President, Global Unichip