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Productivity Tools

Boost Productivity with Products that Complement Our VIP

System-on-chip (SoC) verification is a big job. That's why high-level verification languages like e and SystemVerilog were developed along with companion methodologies like the Universal Verification Methodology (UVM). But language and methodology only take you so far.

Cadence provides additional productivity-boosting tools to help you configure, run, and analyze your design. With these products, you get up and running quickly and shorten your overall verification project.

 

 

 

 

PureView

PureView is a graphical cockpit used to configure all our VIP products. Many interface protocols have dozens of configuration options. To match a VIP component to your design, each option needs to be set correctly. It would be time-consuming and error-prone to set every parameter with a text command, but PureView makes it easy.  The tool walks you through a hierarchy of menus to configure a VIP component. It only shows you relevant options based on previous choices and prevents illegal settings. PureView is also used to configure memory model options and TripleCheck tests.

Example PureView menus for PCI Express VIP configuration

TripleCheck for PCI Express

TripleCheck for PCI Express helps you verify that your design complies with the interface specification. This is different than a post-silicon compliance test that measures electrical parameters.  TripleCheck works during pre-silicon logic simulation to stress-test functional behavior. TripleCheck is the third-generation compliance product to be offered by Cadence, delivering an enhanced test suite, coverage model, and verification plan. 

PureView Integration

For quick set-up, TripleCheck is integrated with our PureView solution. When you configure a VIP with PureView, the TripleCheck test suite, coverage model, and vPlan are automatically configured to match the VIP.

Test Suite

TripleCheck provides an extensive library of test sequences to stimulate the design under test. The test library contains directed tests (providing quick checks for common protocol compliance issues) as well as constrained-random test sequences for exhaustive testing to detect corner-case bugs hidden in the design. The tests support error injection in each layer of the protocol stack to check operation of the design when faced with non-compliant stimulus. This combination of directed and constrained-random tests results in high functional coverage, right out of the box.

Coverage Model

Coverage models are provided in both SystemVerilog and e verification languages. These pre-defined coverage models capture all data items and state machine transitions to track and measure verification progress. The coverage models are open and documented, which allows you to extend them with application-specific coverage definitions. 

Verification Plan

TripleCheck provides a verification plan that mirrors the protocol specification. All the requirements in the protocol specification are listed in the plan and organized into the same chapter and paragraph hierarchy.

The vPlan is linked to the coverage model so that the coverage data captured during simulation runs is automatically mapped against the plan. This makes it easy to track verification progress and determine how much work remains. The vPlan is written in XML to enable portability between simulation environments.

In the Cadence® Incisive® Simulation environment, TripleCheck integrates with the Incisive Enterprise Manager tool to enable a number of productivity-boosting features, such as bucket analysis to analyze coverage details and test profiling to sort out unproductive test sequences.

PCI Express Features

Feature Name
Description

Advanced Error Reporting

Stimuli and coverage collection of all applicable error scenarios

Full LTSSM Transitions Stimuli and coverage collection of all LTSSM transitions
Equalization Procedure Stimuli and coverage collection of all aspects of equalization process
Packet Formation Rules Stimuli and coverage collection of all applicable TLPs

Third-Generation Solution

TripleCheck is a third-generation pre-silicon compliance test suite solution. It combines the features from Cadence's other test suite solutions to deliver the most advanced pre-silicon compliance test suite on the market.

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

 

TripleCheck for Ethernet 40G/100G

TripleCheck for Ethernet 40G/100G helps you verify that your design complies with the interface specification. This is different than a post-silicon compliance test that measures electrical parameters. TripleCheck works during pre-silicon logic simulation to stress-test functional behavior. TripleCheck is the third-generation compliance product to be offered by Cadence, delivering an enhanced test suite, coverage model, and verification plan. 

PureView Integration

TripleCheck is integrated with our PureView solution for quick set-up. When you configure a VIP with PureView, the TripleCheck test suite, coverage model, and vPlan are automatically configured to match the VIP.

Test Suite

TripleCheck provides an extensive library of test sequences to stimulate the design under test. The test library contains directed tests (providing quick checks for common protocol compliance issues) as well as constrained-random test sequences for exhaustive testing to detect corner-case bugs hidden in the design. The tests support error injection in each layer of the protocol stack to check operation of the design when faced with non-compliant stimulus. This combination of directed and constrained-random tests results in high functional coverage, right out of the box.

Coverage Model

Coverage models are provided in both SystemVerilog and e verification languages. These pre-defined coverage models capture all data items and state machine transitions to track and measure verification progress. The coverage models are open and documented, which allows you to extend them with application-specific coverage definitions. 

Verification Plan

TripleCheck provides a verification plan that mirrors the protocol specification. All the requirements in the protocol specification are listed in the plan and organized into the same chapter and paragraph hierarchy.

The vPlan is linked to the coverage model so that the coverage data captured during simulation runs is automatically mapped against the plan. This makes it easy to track verification progress and determine how much work remains. The vPlan is written in XML to enable portability between simulation environments.

In the Cadence Incisive Simulation environment, TripleCheck integrates with the Incisive Enterprise Manager tool to enable a number of productivity-boosting features, such as bucket analysis to analyze coverage details and test profiling to sort out unproductive test sequences.

Ethernet 40G/100G Features

Feature Name
Description

Advanced error reporting

Stimuli and coverage collection of all applicable error scenarios

Ethernet frame Stimuli and coverage collection of different packet types and fields
Clause 80,81, and 82 Stimuli and coverage collection of CGMII, XLGMII features, and FSM states
Clause 73 auto-negotiation Stimuli and coverage collection of all arbitration states and transitions

Third-Generation Solution

TripleCheck is a third-generation pre-silicon compliance test suite solution.  It combines the features from Cadence's other test suite solutions to deliver the most advanced pre-silicon compliance test suite on the market.

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments