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Memory Models

Memory Models for verifying SoC memory interfaces such as DDR2, DDR3, DDR4, LPDDR2, LPDDR3, LPDDR4, and Flash interfaces

Verify Memory Interface Functionality and Timing

Memory is a major part of every electronic product. Every system on chip (SoC) contains embedded memories and must also interface with external memory components. The operation of these interfaces impacts both SoC functionality and performance, making memory interface verification a crucial step in the SoC development process.

Cadence® Memory Models are the gold standard for memory interface verification. Used by more than 500 customers, Cadence Memory Models provide support for 6,000 memories spanning 60 memory interface types and 85 memory manufacturers.

Vendor Certification

Memory models for commercial memory components are based on the manufacturer's datasheets and are then provided to the manufacturer for certification. This closed-loop quality control process means that you can trust your simulation results. Models for new external memory standards that do not yet have commercial component providers and models for internal memory standards are based upon the specifications provided by the controlling standards body, such as JEDEC, ONFi, and SD Association. Cadence works closely with our early-adopter customers to ensure the quality of these models.

Accurate Timing Analysis

When memory models represent actual memory chips and modules, the memory models include full timing parameters that support accurate gate-level simulations. Timing specs are conveniently displayed in the PureView tool and can be overridden for what-if analysis.

Second-Source Evaluation

Memory models are inserted into a testbench as generic models that are then associated with a personality file to represent a specific component. This makes it easy to do second-source evaluation of memory components. Just use the same testbench and re-run your simulation with the personality file for the second-source candidate.

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Portfolio

Memory Model PortfolioA cost effective way to incorporate multiple memory models in the same simulation

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DRAM

DDR3 Memory ModelProvides multiple vendor support

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DDR4 Memory ModelSupports 3DS level command decoding

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High Bandwidth Memory (HBM) Memory ModelCan be used 8 times to model a single 8-channel device

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Hybrid Memory Cube (HMC) Memory ModelIndustry's first memory model for HMC

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LPDDR3 Memory ModelSupports multiple densities from 4Gb to 32Gb

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LPDDR4 Memory ModelSupports speeds up to 2133 Mt/s

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LRDIMM Memory ModelProvides configurable DIMM topologies for ranks and components

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DDR4 LRDIMM Memory ModelProvides configurable DIMM topologies

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Wide I/O Memory ModelCan be used four times to model the 4-channel device.

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Wide I/O 2 Memory ModelCan be used four times to model a single slice or eight times to model a 2-slice device

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FLASH

eMMC 4.5 Memory ModelProvides register support for CID/CSD/OCR and Ext_CSD registers

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eMMC 5.0 Memory ModelSupports eMMC command/response protocols

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Flash ONFi 3.0, 4.0 Memory ModelSupports all three interfaces: SDR/NV-DDR/NV-DDR2

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Flash Toggle NAND 2 Memory ModelProvides on-die termination, ODT, support

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Flash PPN DDR Memory ModelSupports low-power/normal-power async/DDR modes of device operation

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SD Card 4.0 Memory ModelSupports 2L-HD mode, half duplex, which doubles data throughput

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UFS 2.0 Memory ModelSupports UTP layer UPIUs: NOP IN/OUT; query request/response; task management request/response

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