Home: IP Portfolio > Verification IP > Memory Models

Memory Models

Memory Models for verifying SoC memory interfaces such as DDR2, DDR3, DDR4, LPDDR2, LPDDR3, LPDDR4, and Flash interfaces

Verify Memory Interface Functionality and Timing

Memory is a major part of every electronic product. Every system on chip (SoC) contains embedded memories and must also interface with external memory components. The operation of these interfaces impacts both SoC functionality and performance, making memory interface verification a crucial step in the SoC development process.

Cadence® Memory Models are the gold standard for memory interface verification. Used by more than 500 customers, Cadence Memory Models provide support for 6,000 memories spanning 60 memory interface types and 85 memory manufacturers.

Vendor Certification

Memory models for commercial memory components are based on the manufacturer's datasheets and are then provided to the manufacturer for certification. This closed-loop quality control process means that you can trust your simulation results. Models for new external memory standards that do not yet have commercial component providers and models for internal memory standards are based upon the specifications provided by the controlling standards body, such as JEDEC, ONFi, and SD Association. Cadence works closely with our early-adopter customers to ensure the quality of these models.

Accurate Timing Analysis

When memory models represent actual memory chips and modules, the memory models include full timing parameters that support accurate gate-level simulations. Timing specs are conveniently displayed in the PureView tool and can be overridden for what-if analysis.

Second-Source Evaluation

Memory models are inserted into a testbench as generic models that are then associated with a personality file to represent a specific component. This makes it easy to do second-source evaluation of memory components. Just use the same testbench and re-run your simulation with the personality file for the second-source candidate.

More Information

Memory Model Portfolio A cost effective way to incorporate multiple memory models in the same simulation

The Memory Model Portfolio is the most cost-effective way to service the majority of memory interface verification needs.

The Memory Model Portfolio enables all the memory models shown in the table below.  A single license enables multiple instances of all the models in a single simulation session. Multiple licenses are needed to enable multiple simultaneous simulation sessions.

Memory ModelDevice Type
SDIO Card Memory
SD Card Card Memory
SD Card 3.0 Card Memory
Cellular SRAM SRAM
Compact Flash Card Memory
eMMC 1.0, 2.0, 3.0, 4.4 Card Memory
Memory Stick Card Memory
MemStick Pro Card Memory
DDR DIMM (DDR Dual Inline Memory Module) DRAM
DDR 1, 2, 3 DRAM
DDR SDRAM DRAM
DDR Synchronous Graphics RAM DRAM
DDR 2 DRAM
Enhanced SDRAM DRAM
FCRAM (Fujitsu Consumer RAM) DRAM
FIFO SRAM
LL DRAM: Low-Latency DRAM DRAM
LPDDR 1,2: Low-Power DDR DRAM
LR DIMM (Load-Reduced DIMM) DRAM
RLDRAM 1,2,3 (Read-Reduced Latency DRAM) DRAM
GDDR 2,3,4 (Graphics DDR) DRAM
DDR Synchronous RAM SRAM
Wide I/O DRAM
Embedded SSRAM Embedded / FPGA
Embedded SSRAM TI Embedded / FPGA
Register File Embedded / FPGA
Delayline Miscellaneous
Scratchpad Miscellaneous
Flash (Basic) Non-Volatile
Flash ONFi Non-Volatile
Flash Toggle NAND Non-Volatile
Flash Toggle NAND2 Non-Volatile
LBA NAND (Logical Block Addressing NAND Flash) Non-Volatile
NAND Flash Non-Volatile
NOR FLASH Spansion Non-Volatile
OneNAND Flash Non-Volatile
PROM (Programmable ROM) Non-Volatile
Pseudo Burst SRAM SRAM
QDR SRAM (Quad Data Rate SSRAM) SRAM
Rambus DRAM DRAM
Rambus Turbo Mode DRAM
Synchronous DRAM DRAM
Synchronous Mask ROM Non-Volatile
Synchronous RAM NEC SRAM
DFI DDR PHY I/F

DDR3 Memory Model

Specification Support

The DDR3 Memory Model supports the JESD79-3 version of the DDR3 SDRAM specification.

Product Highlights

  • Provides DDR functionality and timing check support for precharge, activate, read/write mode, register write, write leveling, ODT checks, power down, self refresh and initializations
  • Supports multiple data widths and densities:  x4 – x16 width; 500M – 8G density
  • Supports multiple speed grades:  800, 1066, 1333, 1600
  • Provides multiple vendor support:  Micron, Elpida, Eorex, Hynix, Nanya, Samsung, and Winbond
  • Supports multiple other functions such as:  state machine and timing checks; DLL change and clock frequency changes; bank groups; write leveling; MPR read training; input data masking; drift read output delay and refresh

DDR4 Memory Model

Specification Support

The DDR4 Memory Model the officially released JESD79-4 Rev 1.0 Specification

Product Highlights

  • Supports 3DS level command decoding
  • Supports 3DS Read/Write commands for 2H/4H/8H combinations
  • Provides DDR functionality and timing check support for precharge, activate, read, write, mode register write, write leveling, ODT checks, power down, self refresh, and initializations
  • Supports multiple data widths and densities:  x4, x8, x16 width; 2Gb to 16Gb density
  • Supports multiple speed grades: 1600, 1866, 2133
  • Provides multiple vendor support:  Micron, Hynix, Samsung
  • Supports multiple other functions such as:  state machine and timing checks; DLL change and clock frequency changes; bank groups; write leveling; MPR read training; input data masking; drift read output delay, and refresh

eMMC 4.5 Memory Model

Specification Support

Supports the eMMC 4.5 specification

Product Highlights

  • Provides register support for CID/CSD/OCR and Ext_CSD registers
  • Supports eMMC command/response protocols
  • Supports high-capacity negotiation for devices larger than 2GB
  • Supports cache read/write operations
  • Supports multiple other functions such as: state machine and timing checks; voltage range checking; context IDs; data tag mechanism; DDR timing; discard command; extended partition types; high-speed 200MHz mode; and others

eMMC 5.0 Memory Model

Specification Support

Supports the eMMC 5.0 and 5.1 specification

Product Highlights

  • Provides register support for CID/CSD/OCR and Ext_CSD registers
  • Supports eMMC command/response protocols
  • Supports high-capacity negotiation for devices larger than 2GB
  • Supports cache read/write operations
  • Supports multiple other functions such as: state machine and timing checks; voltage range checking; context IDs; data tag mechanism; DDR timing; discard command; extended partition types; high-speed 200MHz mode; and others

Flash ONFi 3.0, 4.0 Memory Model

Specification Support

Supports all versions of the Open NAND Flash Interface, the latest being 4.0

Product Highlights

  • Supports CE_n pin reduction that allows multiple devices to be connected to a single "chip enable"
  • Supports all three interfaces: SDR/NV-DDR/NV-DDR2
  • Supports multi-plane read/program/erase/copyback operations
  • Supports multi-plane cache operations: read/program
  • Supports multi-LUN operations for simultaneous read/program/erase

Flash Toggle NAND 2 Memory Model

Specification Support

The model supports toggle NAND DDR 2.0 from vendors including Hynix, Samsung, Toshiba, and SanDisk, etc. The specifications are available from the respective vendors. 

Product Highlights

  • Provides on-die termination, ODT, support
  • Supports differential DQS pins
  • Supports differential rebar pins
  • Supports multiple dies with shared CEbar
  • Supports multiple other functions such as: four planes with two address bits per plane; two planes with writes to two pages each

High Bandwith Memory (HBM) Memory Model

Specification Support

The HBM Memory Model VIP supports single-channel implementation version of the HBM DRAM specification and can be used 8 times to model a single 8-channel device.

Product Highlights

  • Implements internal Wide I/O 2 state machine and performs specified timing checks
  • 128-bit wide data bus. Pseudo channel mode with 64-bit data
  • The model supports a wide range of device densities
  • Differential clock and read/write strobes
  • All bank, per-bank and self-refresh. Refresh timing check

Hybrid Memory Cube (HMC) Memory Model

Specification Support

HMC Rev 1_1 specification is supported.

Product Highlights

  • Transaction callback events on requests and responses to monitor activity at each protocol layer
  • Link layer initialization at power-on

LPDDR3 Memory Model

Specification Support

Supports the officially released JESD 209-3 version of the LPDDR3 specification

Product Highlights

  • Provides DDR functionality and timing check support for precharge, activate, read, write, mode register write, power down, deep power down, self refresh, initializations, and all related timing checks
  • Supports multiple densities: 4Gb to 32Gb 
  • Supports on-die termination
  • Supports partial array self-refresh and per-bank refresh
  • Supports multiple other functions such as: write leveling; CA training, device temperature sensor adaptation

LPDDR4 Memory Model

Specification Support

Our LPDDR4 Memory Model VIP is evolving and supports most of the proposals that are balloted at JEDEC.

Product Highlights

  • Provides DDR functionality and timing check support for precharge, activate, read, write, mode register write, power down, deep power down, self-refresh, initializations, and all related timing checks
  • Supports multiple densities:  4Gb to 32Gb 
  • Supports speeds up to 2133
  • Supports dual channels which can function independently
  • Supports multiple other functions such as: data mask and data bus inversion; on-the-fly burst length; configurable preamble and postamble

LRDIMM Memory Model

Specification Support

Our DDR RDIMM Memory Model VIP supports JEDEC DDR3 SDRAM Registered DIMM Design Specification Revision 0.84, as well as LRDIMM Specification Memory Buffer (Rev 0.95a) and JEDEC DDR3 Register - JESD82-29A for SSTE32882 (the RCD) specification.

Product Highlights

  • Provides configurable DIMM topologies for ranks and components
  • Supports flyby delays:  DIMM to DRAM (for UDIMM); RCD to DRAM (for RDIMM/LRDIMM)
  • Supports address mirroring
  • Supports ECC check bits
  • Supports multiple other functions such as:  core RCD forwarding logic; RCD control word writes; parity as well as multiple DRAM features

DDR4 LRDIMM Memory Model

Specification Support

Our DDR4 LRDIMM Memory Model VIP supports JEDEC DDR4 SDRAM Registered DIMM Design Specification (Rev 0.8) for RDIMM specificaion and follows JEDEC DDR4 Register - DDR4RCD01 - Rev 0.92 for the RCD specification.

Product Highlights

  • Provides configurable DIMM topologies:  DIMM, RCD, DRAM
  • Supports flyby delays:  DIMM to RCD; RCD to DRAM
  • Supports address mirroring
  • Supports configurable DQ maps
  • Supports multiple other functions such as: core RCD forwarding logic; RCD control word writes; and parity as well as multiple DRAM features

Flash PPN DDR Memory Model

Specification Support

The model supports all versions of E2NAND (Hynix) and EFNAND (Samsung), the latest being version 3.0.

Product Highlights

  • Supports low-power/normal-power async/DDR modes of device operation
  • Supports CRC for data read/write in DDR mode
  • Supports scratch pad memory
  • Supports DQS/RE complimentary pns in DDR
  • Provides support for clearing program error lists

SD Card 4.0 Memory Model

Specification Support

The relevant specifications are Part 1 Physical Layer Specification Version 4.00 and Part 1 UHS-II Addendum Version 1.00. Both are available on request from SD Association's Members Site:https://www.sdcard.org/home/

Product Highlights

  • Supports 2L-HD mode, half duplex, which doubles data throughput
  • Supports PHY-link interface
  • Supports data burst streaming, which allows multiple model instances to be connected using a ring connection
  • Supports boot code loading
  • Supports multiple other functions such as: data burst retry; low-power mode; and speed ranges A&B

UFS 2.0 Memory Model

Specification Support

Our UFS Memory Model VIP supports specification version 1.1 and 2.0.

Product Highlights

  • Supports UTP layer UPIUs: NOP IN; NOP OUT; query request/response; task management request/response
  • Supports UCS layer SCSI commands:   READ6/READ10/READ16, WRITE6/WRITE10/WRITE16, Inquiry, Report LUNs, Read Capacity 10, Read Capacity 16, Test Unit Ready, Verify, Start/Stop Unit
  • Supports UFS protocol features:  boot functionality, LUNS and W-LUNS; command interleaving; queue depth of over 32 commands
  • Supports the Cport signaling interface with C-port connections to Unipro device and direct C-port connections to Unipro Host
  • Supports UFS only and full-stack UFS use cases

 

Wide I/O Memory Model

Specification Support

Our Wide I/O SDRAM Memory Model VIP supports single-channel implementation of the officially released JESD229 version of the Wide I/O SDR specification, and can be used four times to model the 4-channel device.

Product Highlights

  • Supports state machine and timing checks
  • Supports data width up to 128-bit, single data rate
  • Supports wide range of device densities
  • Supports differential CK and DQS for future DDR extensions
  • Supports partial array self-refresh and per-bank refresh

Wide I/O 2 Memory Model

Specification Support

Our Wide I/O 2 DDRAM Memory Model VIP supports a single-channel implementation version of the Wide I/O 2 DDR specification, and can be used four times to model a single slice (4-channel device) or eight times to model a 2-slice (8-channel) device. The final official JEDEC specification is not yet available.

Product Highlights

  • Supports state machine and timing checks
  • Supports 64-bit data bus width at double data rate
  • Supports wide range of device densities
  • Supports complimentary data strobe for every 16 data bits
  • Supports partial array self-refresh and per-bank refresh; backdoor reads/writes; comprehensive assertion library; power-on initialization; trace debug and transaction and memory callbacks