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Assertion-Based VIP

Assertion-Based VIP supports the formal analysis of SoC interfaces such as DFI, AMBA AXI, AMBA AHB, AMBA ACE, and OCP

VIP for Comprehensive Formal Analysis

Formal analysis is a mathematical approach to verification that has the unique ability to prove that a design is 100% correct.  This method is tremendously useful, but is limited in the size and types of designs that can be verified.  Still, for IP blocks with bus-style interfaces, it is an ideal verification solution.  

Cadence® Assertion-Based VIP simplifies formal verification through its plug-and-play approach. Just attach the VIP to your design and run – no need for complicated tests and coverage analysis.

 

No Tests Required

With Cadence Assertion-Based VIP, no test creation is required.  Unlike logic simulation that uses test sequences to stimulate a design, a pre-programmed set of "constraints" is supplied with the assertion-based VIP.  These constraints describe the range of all possible stimulus for a given interface specification.  Also, "assertions" in the VIP check the interface signaling to make sure your design is acting in accordance with the protocol specification.  You can start verifying your design in minutes with our assertion-based VIP.

Debug Made Easy

Cadence Assertion-Based VIP works with the Cadence Incisive® Formal Verifier tool to make debug easy. When the VIP detects a design error, Incisive Formal Verifier displays a waveform trace, schematic view, and source code analysis of the bug. This makes it easy to find the root causes of bugs – and fix them!

 

Assertion-Based VIP Video

AMBA 4 ACE Assertion-Based Verification IP (VIP)

Specification Support

Our AXI4 and ACE™ Assertion-Based VIP supports the AMBA® ACE™ Protocol IHI0022D

Product Highlights

  • Supports AXI4 and ACE protocols
  • Provides comprehensive protocol compliance checking for the AXI™ cache coherency extensions (ACE)
  • Features debug capabilities including AXI4- and ACE-specific transaction view

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

AMBA AHB Assertion-Based Verification IP (VIP)

Specification Support

  • The AHB™ Assertion-Based VIP supports the AMBA 2 and AMBA 3 AHB Interface Protocol Specifications
  • The APB™ Assertion-Based VIP is included and supports the AMBA 2, AMBA 3, and AMBA 4 APB Interface Protocol Specifications

Product Highlights

  • Allows AHB-Lite configuration
  • Supports round-robin or user priority based arbitration
  • Supports burst reconstruction after split or a retry response, in addition to early burst termination
  • Allows master to continue after error response
  • Controls maximum length of INCR burst transfer
  • Supports monitoring and driving of locked transactions
  • Controls the burst type supported by master and the response type supported by slave

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

AMBA AXI Assertion-Based Verification IP (VIP)

Specification Support

  • The AXI3 Assertion-Based VIP supports the AMBA AXI protocol v1.0 and v2.0 and AXI as defined in the AMBA AXI protocol specification
  • The APB Assertion-Based VIP is included and supports the AMBA 2, AMBA 3, and AMBA 4 APB interface protocol specifications

Product Highlights

  • Supports all legal data and address widths
  • Supports sending of data before address transactions 
  • Supports interleaving of read/write data, wherever applicable
  • Supports monitoring and driving of all exclusive transactions
  • Supports monitoring and driving of locked transactions 
  • Supports low-power interface 

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

DFI Assertion-Based Verification IP (VIP)

Specification Support

Supports the DDR PHY Interface (DFI) protocol standard v. 3.0

Product Highlights

  • Can be configured in master, slave, or monitor mode
  • Master mode provides DDR memory controller capabilities to verify compliance of a DDR PHY
  • Slave mode provides DDR PHY capabilities to verify compliance of a DDR memory controller
  • Monitor mode provides passive checker capabilities to verify compliance of the memory controller to DDR PHY interface

Supported Design-Under-Test Configurations

Controller PHY Hub/Switch
Full Stack Controller Only PHY Only

OCP Assertion-Based Verification IP (VIP)

Specification Support

Our OCP Assertion-Based VIP supports the OCP2.2 and OCP3.0 interface protocol specifications

Product Highlights

  • Supports multiple threads and tag IDs
  • Supports 2-D burst transactions 
  • Supports clock enabling 
  • Supports non-blocking flow control
  • Supports DUT with non-combinational response

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only