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Assertion-Based VIP

Assertion-Based VIP supports the formal analysis of SoC interfaces such as DFI, AMBA AXI, AMBA AHB, AMBA ACE, and OCP

VIP for Comprehensive Formal Analysis

Formal analysis is a mathematical approach to verification that has the unique ability to prove that a design is 100% correct.  This method is tremendously useful, but is limited in the size and types of designs that can be verified.  Still, for IP blocks with bus-style interfaces, it is an ideal verification solution.  

Cadence® Assertion-Based VIP simplifies formal verification through its plug-and-play approach. Just attach the VIP to your design and run – no need for complicated tests and coverage analysis.

 

No Tests Required

With Cadence Assertion-Based VIP, no test creation is required.  Unlike logic simulation that uses test sequences to stimulate a design, a pre-programmed set of "constraints" is supplied with the assertion-based VIP.  These constraints describe the range of all possible stimulus for a given interface specification.  Also, "assertions" in the VIP check the interface signaling to make sure your design is acting in accordance with the protocol specification.  You can start verifying your design in minutes with our assertion-based VIP.

Debug Made Easy

Cadence Assertion-Based VIP works with the Cadence Incisive® Formal Verifier tool to make debug easy. When the VIP detects a design error, Incisive Formal Verifier displays a waveform trace, schematic view, and source code analysis of the bug. This makes it easy to find the root causes of bugs – and fix them!

 

Assertion-Based VIP Video

AMBA 4 ACE Assertion-Based Verification IP (VIP)

Specification Support

Our AXI4 and ACE™ Assertion-Based VIP supports the AMBA® ACE™ Protocol IHI0022D

Product Highlights

  • Supports AXI4 and ACE protocols
  • Provides comprehensive protocol compliance checking for the AXI™ cache coherency extensions (ACE)
  • Features debug capabilities including AXI4- and ACE-specific transaction view

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

AMBA ACE-SYS Assertion-Based Verification IP (VIP)

Specification Support

The ACE-SYS ABVIP supports issue IHI0022D and IHI0022E of AMBA AXI and ACE Protocol Specification. 

The specifications for AMBA are available at: http://www.arm.com/products/system-ip/amba/amba-open-specifications.php

Product Highlights

Feature Name
Description

Data and address widths

Supports all legal data and address widths

Protocol transaction types  Supports all read and write transactions 
Data before address mode  Supports sending data before address transactions 
Read interleaving  Supports interleaving of read data 
Exclusive access  Supports monitoring and driving of all exclusive transactions 
Snoop transactions  Supports monitoring and driving of all snoop transactions 
Barrier transactions  Supports monitoring and driving of barrier transactions
ACE-Lite interface  Supports ACE-Lite interface with or without DVM  
DVM messages  Supports monitoring and driving of DVM transactions 
Low power interface Supports low power interface 

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

AMBA AHB Assertion-Based Verification IP (VIP)

Specification Support

  • The AHB™ Assertion-Based VIP supports the AMBA 2 and AMBA 3 AHB Interface Protocol Specifications
  • The APB™ Assertion-Based VIP is included and supports the AMBA 2, AMBA 3, and AMBA 4 APB Interface Protocol Specifications

Product Highlights

  • Allows AHB-Lite configuration
  • Supports round-robin or user priority based arbitration
  • Supports burst reconstruction after split or a retry response, in addition to early burst termination
  • Allows master to continue after error response
  • Controls maximum length of INCR burst transfer
  • Supports monitoring and driving of locked transactions
  • Controls the burst type supported by master and the response type supported by slave

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

AMBA ATB Assertion-Based Verification IP (VIP)

Specification Support

The ATB ABVIP supports the AMBA ATB protocol v1.0 and v1.1 as defined in the AMBA ATB protocol specification, ARM IHI 0032B.

The specifications for AMBA are available at:  http://www.arm.com/products/system-ip/amba/amba-open-specifications.php

Product Highlights

Feature
Description

Protocol version

Configurable as ATB v1.0 or v1.1

Protocol parameters

Supports configurable data, bytes, and id widths

Flushing Supports flushing protocol feature
Trace Storage  Configurable master internal trace storage, absent or present 
Flow Control Provides valid/ready liveness checks for data and flush

X-propagation

Configurable support for X-propagation checks

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

AMBA AXI Assertion-Based Verification IP (VIP)

Specification Support

  • The AXI3 Assertion-Based VIP supports the AMBA AXI protocol v1.0 and v2.0 and AXI as defined in the AMBA AXI protocol specification
  • The APB Assertion-Based VIP is included and supports the AMBA 2, AMBA 3, and AMBA 4 APB interface protocol specifications

Product Highlights

  • Supports all legal data and address widths
  • Supports sending of data before address transactions 
  • Supports interleaving of read/write data, wherever applicable
  • Supports monitoring and driving of all exclusive transactions
  • Supports monitoring and driving of locked transactions 
  • Supports low-power interface 

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

AMBA AXI4-Stream Assertion-Based Verification IP (VIP)

Specification Support

The AXI4-Stream ABVIP supports the AMBA4 AXI4-Stream protocol v1.0 specification.

The specifications for AMBA are available at:  http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0051a/index.html

Product Highlights

Feature
Description

Data and address widths

Supports all legal data and address widths

TID, TDEST and TUSER widths Supports all legal TID, TDEST and TUSER widths 
Transfer interleaving Supports transfer interleaving functionality 
Transfer ordering  Supports transfer ordering functionality 
Data merging and packing Supports data merging of different transfers 
User signaling  Supports user defined sideband signal 
Data stream transfers  Supports data stream transfer between master and slave 

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

AMBA CHI Assertion-Based Verification IP (VIP)

Specification Support

The CHI ABVIP supports the AMBA CHI protocol as defined in the AMBA 5 CHI architecture specification, Issue A.

The specifications for AMBA are available at:  http://www.arm.com/products/system-ip/amba/amba-open-specifications.php

Product Highlights

Feature
Description

Protocol parameters

Supports all protocol parameters, for example, data width

Target ID remap Supports target ID remap 
Snoop broadcast vector Configurable support for snoop broadcast vector
Exclusive access  Configurable checking of all exclusive transactions 
Node types Configurable as any of eight node types 
Protocol layers  Checks for protocol, network, and link layers 
Request retry  Full support for request retry 

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

AMBA CHI SYS Assertion-Based Verification IP (VIP)

Specification Support

The CHI SYS ABVIP supports the AMBA CHI architecture as defined in the AMBA CHI architecture specification, ARM IHI 0050A.

The specifications for AMBA are available at:  http://www.arm.com/products/system-ip/amba/amba-open-specifications.php

Product Highlights

Feature
Description

System parameters

Specify number of addresses and requesting nodes to monitor

Verify RN or ICN Automatic assert/assume configuration via parameter 
Optional interface Facilitates more accurate cache state tracking when possible
Protocol transaction types  Supports all read, write, and snoop transactions and responses 

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

DDR Assertion-Based Verification IP (VIP)

Specification Support

The DDR ABVIP supports the JEDEC DDR SDRAM STANDARD (JESD79F) protocol specification.

The specifications for DDR are available at: http://www.jedec.org/sites/default/files/docs/JESD79F.pdf

Product Highlights

Feature name

Description

Data and address widths Supports all legal data (DQ) and address widths configuration
Bidirectional data strobe Supports sending of data before address transactions 
Configurable burst length Supports different burst lengths of 2, 4, or 8
Configurable CAS latency Supports all legal CAS latency
Configurable mode register Supports mode register set command
Auto refresh and self refresh Supports configurable auto refresh and self refresh mode 
Auto precharge cycle Supports all legal value of the auto precharge for each burst 
Configurable active bank period Supports different period of active bank to another active bank

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

DDR2 Assertion-Based Verification IP (VIP)

Specification Support

The DDR2 ABVIP supports the JEDEC Standard DDR2 SDRAM (JESD79-2F) protocol specification.

The specifications for DDR2 are available at: http://www.jedec.org/sites/default/files/docs/JESD79-2F.pdf

Product Highlights

Feature name

Description

Data and address widths Supports all legal data (DQ) and address widths configuration
Bank address widths Supports all legal bank address widths configuration
Configurable CKE widths Supports  configurable CKE minimum pulse width 
Burst mode operation Supports different burst lengths of 4 or 8
Configurable CAS latency Supports all legal CAS latency
Mode register set value Supports mode register set command
Extended mode register  Supports extended mode register command
Auto precharge cycle Supports all legal values of the auto precharge for each burst
Additive latency Supports different additive latency value 
RAS 2 CAS delay Supports different values of RAS to CAS delay
Configurable active bank period Supports different period of active bank to another active bank

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

DDR3 Assertion-Based Verification IP (VIP)

Specification Support

The DDR3 ABVIP supports the JEDEC Standard DDR3 SDRAM (JESD79-3E) protocol specification.

The specifications for DDR3 are available at: http://www.jedec.org/sites/default/files/docs/JESD79-3E.pdf

Product Highlights

Feature name

Description

Address and Bank address widths Supports all legal address and bank address widths
Configurable CKE widths Supports  configurable CKE minimum pulse width 
Burst mode operation Supports different burst lengths of 4 or 8
Configurable CAS latency Supports all legal CAS latency
Mode register set value Supports mode register set command
Extended mode register  Supports extended mode register command
Auto precharge cycle Supports all legal values of the auto precharge for each burst
Additive latency Supports different additive latency value 
RAS 2 CAS delay Supports different values of RAS to CAS delay
Power down entry/exit Supports power down entry to exit timing
ODT(On-Die Termination) Supports ODT features
CWL (CAS write latency) Supports CWL per clock bin
Configurable active bank period Supports different period of active bank to another active bank

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

DFI Assertion-Based Verification IP (VIP)

Specification Support

Supports the DDR PHY Interface (DFI) protocol standard v. 3.0

Product Highlights

  • Can be configured in master, slave, or monitor mode
  • Master mode provides DDR memory controller capabilities to verify compliance of a DDR PHY
  • Slave mode provides DDR PHY capabilities to verify compliance of a DDR memory controller
  • Monitor mode provides passive checker capabilities to verify compliance of the memory controller to DDR PHY interface

Supported Design-Under-Test Configurations

Controller PHY Hub/Switch
Full Stack Controller Only PHY Only

LPDDR Assertion-Based Verification IP (VIP)

Specification Support

The LPDDR ABVIP supports the JEDEC LPDDR SDRAM STANDARD (JESD209B) protocol specification.

The specifications for LPDDR are available at: http://www.jedec.org/sites/default/files/docs/JESD7209B.pdf

Product Highlights

Feature name

Description

Data and address widths Supports all legal data and address widths configuration
Configurable burst length Supports different burst lengths of 2, 4, or 8
Deep power down  Supports power down and deep power down
Clock stop Supports clock stop feature
Configurable CAS latency Supports all legal CAS latency
Configurable mode register Supports mode register set command
CKE pulse width Supports CKE minimum pulse width configuration
Auto refresh and self refresh Supports configurable auto refresh and self refresh mode 
Auto precharge cycle Supports all legal values of the auto precharge for each burst 

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

LPDDR2 Assertion-Based Verification IP (VIP)

Specification Support

The LPDDR2 ABVIP supports the JEDEC Standard LPDDR2 SDRAM (JESD209-2E) protocol specification.

The specifications for LPDDR2 are available at: http://www.jedec.org/sites/default/files/docs/JESD209-2E.pdf

Product Highlights

Feature name

Description

Data and address widths Supports all legal data and address widths configuration
Bank address widths Supports all legal bank address widths configuration
LPDDR2 types Supports different LPDDR2 types (S4, S2 and NVM)
Deep power down  Supports power down and deep power down
Clock stop Supports clock stop feature
Configurable CKE widths Supports  configurable CKE minimum pulse width
Burst mode operation Supports different burst lengths of 4, 8 or 16 
Configurable CAS latency Supports all legal CAS latency
Mode register set value Supports mode register set command
Auto precharge cycle Supports all legal values of the auto precharge for each burst 
Additive latency Supports different additive latency value
RAS 2 CAS delay Supports different value of RAS to CAS delay
Configurable active bank period Supports different period of active bank to another active bank                     

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

LPDDR3 Assertion-Based Verification IP (VIP)

Specification Support

The LPDDR3 ABVIP supports the JEDEC Standard LPDDR3 (JESD209-3) protocol specification.

The specifications for LPDDR3 are available at: http://www.jedec.org/standards-documents/results/jesd209-3

Product Highlights

Feature name

Description

Data and address widths Supports all legal data and address widths configuration
Configurable CKE widths Supports  configurable CKE minimum pulse width 
Read/Write latency Supports different Read/Write latency 
Deep power down  Supports power down and deep power down
Clock stop Supports clock stop feature
Configurable CAS latency Supports all legal CAS latency
Mode register Supports mode register command period configurability
Auto precharge cycle Supports all legal values of the auto precharge for each burst 
Additive latency Supports different additive latency value
RAS 2 CAS delay Supports different value of RAS to CAS delay
Power down entry/exit Supports power down entry to exit timing
ODT(On-Die Termination) Supports ODT features
CWL (CAS write latency) Supports CWL per clock bin
Configurable Active bank period Supports different period of active bank to another active bank                     

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

OCP Assertion-Based Verification IP (VIP)

Specification Support

Our OCP Assertion-Based VIP supports the OCP2.2 and OCP3.0 interface protocol specifications

Product Highlights

  • Supports multiple threads and tag IDs
  • Supports 2-D burst transactions 
  • Supports clock enabling 
  • Supports non-blocking flow control
  • Supports DUT with non-combinational response

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

SDRAM Assertion-Based Verification IP (VIP)

Specification Support

The SDRAM ABVIP supports the JEDEC SDR SDRAM STANDARD (JEDEC No.21-C) protocol specification.

The specifications for SDRAM are available at: http://www.jedec.org/

Product Highlights

Feature name

Description

Data and address widths Supports all legal data and address widths configuration
Burst Read/Write Supports different types of burst Read/Write operations 
Configurable burst length Supports different burst lengths of 2, 4, or 8 
Configurable CAS Latency  Supports all legal CAS latency
Multibank operation Supports multibank operations
Configurable Mode register Supports Mode register set command
Auto Refresh and Self Refresh Supports configurable auto refresh and self refresh mode
Auto precharge cycle Supports all legal values of the auto precharge for each burst 
Power Down Supports power down mechanism
Configurable Active bank period Supports different period of active bank to another active bank                     

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only