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Accelerated VIP

Accelerated VIP supports hardware acceleration of SoC interfaces such as USB, PCI Express, Ethernet, MIPI, AMBA AXI, AMBA AHB, and AMBA ACE

Speeding Verification on Hardware Accelerators

Sometimes chips are just too big to verify with logic simulation software. SoCs comprised of tens of millions of logic gates will bog down software simulators, even when running on the fastest servers.

Simulating big designs requires hardware-assisted verification, an approach that uses special-purpose hardware, like Cadence® Palladium® XP systems, to dramatically boost simulation performance. 

Just as simulation VIP simplifies traditional logic simulation, accelerated VIP makes hardware-assisted verification easier and more productive.

Usage Options

Cadence Accelerated VIP enable two popular methods of hardware-assisted verification: simulation acceleration and embedded testbench.

Simulation Acceleration

In simulation acceleration, the Cadence Palladium XP system works in conjunction with the Cadence Incisive® Simulator to divide up the simulation task.  The Palladium XP runs the design under test while the Incisive simulator runs the testbench. Accelerated VIP is inserted for each of the standard interfaces in the design with the testbench interface running on Incisive and the acceleration-optimized core running on the Palladium XP.  Most of the testbench components employed in simulation can be reused, which saves set-up time and preserves the controllability and observeability of traditional logic simulation. With this approach, performance is often up to 1000X faster than logic simulation.

Embedded Testbench

With the embedded testbench approach, both the test environment and the design under test run in the Palladium XP system. This results in huge performance gains – typically 10,000X to 100,000X faster than logic simulation. That kind of speed enables the verification of software along with the hardware design. This enables hardware/software integration bugs to be efficiently discovered and fixed – a task that would be nearly impossible to manage otherwise. To facilitate the embedded testbench approach, application software is often used to run tests and monitor results.

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AMBA 4 ACE Accelerated VIP

Specification Support

This VIP supports specification versions: AMBA® 4 ACE™ and ACE-Lite

Product Highlights

  • Generate and drive bus traffic as an ACE master
  • Respond to bus traffic as an ACE slave 

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only


Usage Options

Simulation Acceleration Embedded Testbench

AMBA AXI Accelerated VIP

Specification Support

The VIP supports specification versions: AMBA AXI3, AXI4, and AXI4-Lite

Product Highlights

  • Generate and drive bus traffic as an AXI™ master

  • Respond to bus traffic as an AXI slave

  • The AXI AVIP supports all types of AXI transactions, including:

    • Unaligned transfers
    • Narrow transfers
    • Interleaved transactions
    • Outstanding transactions
    • Receipt of out-of-order transactions

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only


Usage Options

Simulation Acceleration EmbeddedTestbench

AMBA AHB Accelerated VIP

Specification Support

This VIP supports specification versions: AMBA 3 AHB-Lite specification

Product Highlights

  • Generate and drive bus traffic as an AHB™ master 
  • Respond to bus traffic as an AHB slave
  • Support batching mode in AHB master
  • Support data bus widths of 32, 64, and 128 bits
  • The AHB AVIP supports all types of AHB transactions, including:
    • Unaligned transfers
    • Narrow transfers
    • Interleaved transactions
    • Outstanding transactions
    • Receipt of out-of-order transactions

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only


Usage Options

Simulation Acceleration EmbeddedTestbench

AMBA APB Accelerated VIP

Specification Support

This VIP supports specification versions: AMBA APB™ protocol specification, version 2

Product Highlights

  • Generate and drive bus traffic as an APB master 
  • Respond to bus traffic as an APB slave
  • Support batching mode in APB master

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only


Usage Options

Simulation Acceleration EmbeddedTestbench

Ethernet 10/100/1G/10G Accelerated VIP

Specification Support

This VIP supports specification versions: MII, GMII, RGMII, XGMII, and XSBI

Product Highlights

10G MAC: Full duplex operation

  • Dual-edge 32-bit and single-edge 64-bit XGMII interface to the PHY Interrupt generation on completion of receive and transmit
  • Optional automatic preamble, pad, and cyclic redundancy check (CRC) generation on transmitted frames
  • Optional non-standard preamble compatibility on received frames
  • Promiscuous mode where all valid received frames are forwarded
  • PHY management through the MDIO interface
  • Jumbo frames of up to 10,240 bytes
  • Pause frames
  • 802.1Q VLAN tagging with recognition of incoming VLAN and priority tagged frames 802.1Qbb priority-based flow control
  • Configurable inter-packet gaps (IPG)
  • Limited support for 802.3az Energy Efficient Ethernet (EEE)

10G PHY (PCS):

  • Connects to a 10Gb SerDes using a 16-bit, 32-bit, and 64-bit PCS interface
  • 64/66B encoding and decoding with support for all reserved codes and signal ordered set
  • Data scrambler on transmit path and de-scrambler on receive path
  • Optional MDIO interface
  • Pseudo-random test pattern generator and error checker with programmable seeds
  • PRBS31 test pattern generator and error checker
  • Square wave test pattern generator
  • PRBS9 test pattern generator
  • Optional support for forward error correction (FEC)
  • Limited support for EEE 

1G MAC (1G/10M/100M):

  • 10, 100 and 1000Mbps operation
  • Full- and half-duplex operation
  • Statistics counter registers for RMON/MIB RGMII
  • Automatic pad and CRC generation on transmitted frames
  • Frame extension and frame bursting at 1000Mbps in half-duplex mode
  • MDIO interface for PHY management
  • Jumbo frames up to 10,240 bytes
  • Pause frames
  • 802.1Q VLAN tagging with recognition of incoming VLAN and priority tagged frames 802.1Qbb priority-based flow control
  • Configurable IPG

 

40G and 100G MAC Features

 

  • XLGMII interface for Ethernet 40G
  • CGMII interface for Ethernet 100G
  • 64/128/192 bit configurable XLGMII/CGMII to the Physical layer
  • Full duplex operation
  • Automatic preamble, pad, and CRC generation on transmitted frames
  • Jumbo frames of up to 9K bytes
  • Pause frames
  • 802.1Q VLAN tagging with recognition of incoming VLAN and priority tagged frames
  • 802.1Qbb priority-based flow control

 

Other Supported Features:

  • The Ethernet AVIP supports all types of Ethernet transactions, including:

- Ethernet v2 frames, Ethernet 802.3 frames

- Pause frames

- Priority pause frames

- Jumbo frames

- VLAN tagged frames

 

Supported Design-Under-Test Configurations

MAC PHY Hub/Switch
Full Stack Controller Only PHY Only


Usage Options

Simulation Acceleration Embedded Testbench

HDMI 1.4 Accelerated VIP

Specification Support

This VIP supports specification versions: 1.3a and 1.4b

Product Highlights

Supported HDMI 1.4b features:

  • All extended resolution frames
  • All HDMI 3D frame format types, including:
    • Frame packing (for both progressive and interlaced frame types)
    • Side-by-side—half
    • Top and bottom
    • Field alternative
    • Line alternative
    • Side-by-side—full
    • L+depth 
    • L+depth+graphics+graphicsdepth

Supported HDMI 1.3a features:

  • All types of data islands
  • All video frame types
  • All VIC values listed in CEA-861-E
  • Support for full 32KB E-EDID address space 
  • CEC channel
  • HDCP authentication/key exchange over I2C

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only


Usage Options

Simulation Acceleration Embedded Testbench

I2C Accelerated VIP

Specification Support

This VIP supports specification versions: 

  • I2C BFM Requirement Specification, Version 0.9 — 27 August 2012 
  • I2C Bus Specification and User Manual, Rev. 03 — 19 June 2007

Product Highlights

  • BFM can operate as receiver or transmitter in both master or slave modes
  • Fully configurable I2C packets:
    • Standard-mode, Fast-mode, Fast-mode Plus, High-speed mode for both master and slave modes
    • START, STOP, REPEATED START generation, ACKNOWLEDGE, NOT ACKNOWLEDGE generation/detection in master mode
    • START, STOP, REPEATED START detection, ACKNOWLEDGE, NOT ACKNOWLEDGE generation/detection in slave mode
    • Multi-master topology support: synchronization, arbitration, configurable master mode
  • General call support in both master and slave modes
  • 7-bit and 10-bit addressing is supported in both master and slave modes
  • START byte detection in slave mode
  • Master BFM supports sending software reset via I2C
  • Slave BFM can issue clock stretching
  • Master BFM can manage clock stretching

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only


Usage Options

Simulation Acceleration Embedded Testbench

I2S Accelerated VIP

Specification Support

This VIP supports specification versions:

  • I2S BFM Requirement Specification, Version 0.7 – 19 Sep 2012 
  • I2S Bus Specification, Philips Semiconductors –  5 June 1996

Product Highlights

  • Configurable to I2S transmitter or I2S receiver
  • Configurable to I2S master or I2S slave
  • Embedded testbench mode supports:
    • Descriptor-based programming model
    • Scalable internal memory for program and local data
    • AHB slave interface providing full register access and internal memory access
    • DMA and DMA scatter-gather capabilities via AHB master interface
    • Incremental and pseudo-random data generation
    • Configurable hardware and software start/stop conditions
    • Support for simple and embedded programming loops
    • IRQ with maskable interrupt status registers

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only


Usage Options

Simulation Acceleration Embedded Testbench

Keypad Accelerated VIP

Specification Support

This VIP supports specification version: Keypad BFM Requirement Specification, Version 0.4 –19 July 2012

Product Highlights

  • Supports 8x8 KEYPAD matrix 
  • Embedded testbench mode supports:
    • Descriptor-based programming model
    • Internal registers for configuration
    • Scalable internal memory for program and local data
    • AHB slave interface providing full register access and internal memory access
    • Configurable hardware and software start/stop conditions
    • IRQ with maskable interrupt status registers

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only


Keypad Options

Simulation Acceleration Embedded Testbench

MIPI CSI-2 Accelerated VIP

Specification Support

This VIP supports specification versions:

  • MIPI Alliance Specification for Camera Serial Interface 2 (CSI-2), Version 1.01.00 Revision 0.04 – 2 April 2009
  • CSI-2 BFM Requirement Specification, Version 0.10 – 9 July 2012

Product Highlights

  • Fully configurable CSI-2 packets in peripheral mode
  • Embedded digital model of D-PHY
  • Error injection in peripheral mode and error detection in host mode – supporting CSI-2 level (ECC, CRC) protocol error detection
  • Embedded testbench mode supports:
    • Descriptor-based programming model
    • Scalable internal memory for program and local data
    • AHB slave interface providing full register access and internal memory access
    • DMA and DMA scatter-gather capabilities via AHB master interface
    • Incremental and pseudo-random data generation
    • Configurable hardware and software start/stop conditions
    • Support for simple and embedded programming loops
    • IRQ with maskable interrupt status registers

Supported Design-Under-Test Configurations

Host Peripheral Hub/Switch
Full Stack Controller Only PHY Only


Usage Options

Simulation Acceleration Embedded Testbench

MIPI DBI Accelerated VIP

Specification Support

This VIP supports specification versions: 

  • DBI BFM Requirement Specification, Version 0.6 – 18 July 2012
  • MIPI Alliance Standard for Display Bus Interface, Version 2.0 - 16 November 2005 
  • MIPI Alliance Standard for Display Command Set, Version 2.0 – 16 November 2005

Product Highlights

  • Type-B and Type-C interface support
  • Supports the whole DCS command set
  • Configurable data width to 8,9,16,18 bits in Type-B mode
  • Configurable length of read/write cycle (each byte is either 8, 9, or 16 write cycles) in Type-C mode
  • Support for break and pause sequences in Type-C mode
  • Embedded testbench mode supports:
    • Descriptor-based programming model
    • Scalable internal memory for program and local data
    • AHB slave interface providing full register access and internal memory access
    • DMA and DMA scatter-gather capabilities via AHB master interface
    • Configurable hardware and software start/stop conditions
    • IRQ with maskable interrupt status registers

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only


Usage Options

Simulation Acceleration Embedded Testbench

MIPI DSI Accelerated VIP

Specification Support

This VIP supports specification versions:

  • DSI BFM Requirement Specification, Version 0.5 – 22 May 2012
  • MIPI Alliance Specification for Display Serial Interface (DSI), Draft Version 1.01.00 Release 11 - 21 February 2008

Product Highlights

  • Multi virtual-channel support in peripheral mode
  • Fully configurable DSI packets in host mode
  • Embedded digital model of D-PHY
  • Additional RGB 8:8:8 interface that can be connected directly to display module
  • Configurable to DSI host or DSI peripheral
  • Bus turnaround support in both host and peripheral mode
  • Error injection in host mode and error detection in peripheral mode – supporting both DSI level (ECC, CRC) and low-level protocol error detection
  • Embedded testbench mode supports:
    • Descriptor-based programming model
    • Scalable internal memory for program and local data
    • AHB slave interface providing full register access and internal memory access
    • DMA and DMA scatter-gather capabilities via AHB master interface
    • Incremental and pseudo-random data generation
    • Configurable hardware and software start/stop conditions
    • Support for simple and embedded programming loops
    • IRQ with maskable interrupt status registers

Supported Design-Under-Test Configurations

Host Peripheral Hub/Switch
Full Stack Controller Only PHY Only


Usage Options

Simulation Acceleration Embedded Testbench

PCI Express Gen2/Gen3 Accelerated VIP

Specification Support

This VIP supports specification version: PCI Express 3.0

Product Highlights

  • 2.5/5/8GT/s speeds
  • 8/16/32-bit PIPE interface

  • Serial interface

  • Configurations up to 8 lanes

  • Power management

  • Complete set of configuration/status registers

  • Link equalization

  • Supports single-root I/O virtualization (SR-IOV)

Supported Design-Under-Test Configurations

Root Complex End Point Hub/Switch
Full Stack Controller Only PHY Only


Usage Options

Simulation Acceleration Embedded Testbench

User Feedback

“As Cadence promised, our validation environment now runs hundreds of times faster than with simulation. Accelerated VIP running on the Palladium XP increased my team’s productivity by 100%. It also enabled us to find bugs we were unable to reach using simulation.”

– Tony Gladvin George, Verification Engineer, Samsung

SATA 3G/6G Accelerated VIP

Specification Support

This VIP supports specification versions: 

  • Serial ATA Specification 3.0
  • ATA Command Set specification, ATA8 version

Product Highlights

  • SATA device disk support for the following class of ATA commands (ATA-8):
    • PIO read and write
    • DMA read and write
    • Non-data commands
    • Queued DMA commands

Supported Design-Under-Test Configurations

Host Device Port Multiplier
Full Stack Controller Only PHY Only


Usage Options

Simulation Acceleration Embedded Testbench

SIMCARD Accelerated VIP

Specification Support

This VIP supports specification version: SIM BFM Requirement Specification, Version 0.7 –14 August 2012

Product Highlights

  • Synthesizable BFM-compliant with ISO/IES 7816-3 standard that supports card mode only (slave)
  • Internal registers for configuration
  • Configurable T0/T1 protocol parameters
  • Supports direct/inverse mode data convention
  • Supports complete activation/deactivation sequence
  • Integrated card state monitor register
  • Error injection for sent packets and error detection for received packets
  • Embedded testbench mode supports:
    • Descriptor-based programming model
    • Scalable internal memory for program and local data
    • AHB slave interface providing full register access and internal memory access
    • DMA and DMA scatter-gather capabilities via AHB master interface
    • Incremental and pseudo-random data generation
    • Configurable hardware and software start/stop conditions
    • IRQ with maskable interrupt status registers

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only


Usage Options

Simulation Acceleration Embedded Testbench