Verify SoC Designs Faster, More Thoroughly, and with Less Effort Using Proven Cadence Verification IP
Specifications for standard interface protocols are often hundreds of pages long. Deciphering these specifications and accurately modeling the protocols is a huge development effort requiring deep technical knowledge. By using production-proven Cadence® Verification IP (VIP), your system-on-chip (SoC) designs can be verified faster, more thoroughly, and with less effort.
Cadence is the industry VIP leader with products supporting more than 40 communication protocols and 60 memory interfaces. Cadence VIP fits into nearly every verification environment with support for all major simulators and verification languages. Our VIP delivers the advanced features that you need to maximize your productivity and keep projects moving forward.
A Proven Solution
There is a good chance that the devices you use every day were verified using Cadence VIP. In fact, more than 500 customers have trusted the Cadence VIP Catalog to verify thousands of designs spanning every type of electronic product.
Read what people say about Cadence VIP
The HDMI 2.0 Verification IP provided by Cadence enabled a small verification team to deliver reliable results within very tight schedule constraints. By reducing the effort required to develop a verification solution, our engineers were able to focus on other tasks crucial to project completion. As a result, we were able to create the type of high-quality and reliable design expected by our customers.
– Larry Porter, Verification Manager, Display Products Division, STMicroelectronics
Cadence USB 3.0 Verification IP has enabled us to thoroughly verify that our designs comply with the USB 3.0 specification, and this new SSIC product demonstrates the company’s commitment to supporting engineers working with this key protocol. By supporting all popular verification methodologies and simulators, Cadence VIP has enabled GUC to support our diverse customer base with high-quality SoC and IP verification coverage.
– James Cheng, Senior Vice President, Global Unichip
As a leading ASIC and SIP (silicon intellectual property) provider, Faraday has been committed to enabling customers to realize their ideas in silicon in a timely manner. We adopted the Cadence VIP solution for its maturity, full feature set, and support. With the adoption, Faraday can provide customers with comprehensive SoC- and IP-level verification coverage.
– Ken Liao, R&D Associate VP, Faraday
HiSilicon is a leader in ASICs and solutions for communication networks and digital media. Delivering advanced multi-core ARM® SoCs to our customers requires leading IC design technologies. Cadence VIP for AXI4 and ACE™ enables us to quickly and efficiently deliver bug-free SoC designs.
– Ting Lei, Director of Cloud Computing, HiSilicon
“CEVA is the world’s leading licensor of DSP cores and platform solutions for the mobile, digital home, and networking markets. Our proprietary FIC bus delivers the right balance of features needed to deliver optimized designs. Flexible Cadence VIP for AXI™ gives us the ability to adapt it to our unique application and exhaustively verify the bus interconnects. This cut our verification effort from six months to three weeks.”
– Richard Kingston, Director of Marketing & Investor Relations, CEVA Inc.
"Wipro has been consistently enabling semiconductor companies to reduce verification time and increase coverage parameters through its next-generation frameworks and market-proven end-to-end verification services. Our partnership with Cadence has played an instrumental role in fulfilling the IP verification needs of our customers. We chose PCIe Gen3 VIP along with TripleCheck by Cadence to achieve a comprehensive solution that gives us the fastest path to IP verification closure."
– A. Vasudevan, VP Semiconductor and Systems, Wipro
"AppliedMicro values working with leading IP providers, like Cadence, to help us achieve our design requirements in the most cost-effective manner. To get to market quickly with lower risk of integration errors, we chose Cadence Verification IP designed for seamless integration into our advanced SystemVerilog design and verification methodology. Cadence's performance and integration gives us confidence that our end-products will properly interoperate with these industry-standard interfaces."
– Amal Bommireddy, Vice President of Engineering, AppliedMicro
"Cadence SuperSpeed USB VIP has helped PLDA to be one of the first IP vendors to reach the market, while ensuring it offers among the highest quality products available. Using Cadence VIP has enabled PLDA to achieve significantly greater functional coverage results."
– Stephane Hauradou, Chief Technology Officer, PLDA
"When faced with the important decision as to which IP vendor has the most reputable and silicon-proven PCI Express IP, Denali (now Cadence) was the preferred vendor that met our critical high-throughput and feature requirements. We rely on Cadence high-quality, interoperable design and verification IP solutions and excellent customer support to meet the PCIe 2.0 and IOV specifications, and our product development timeframes, and to help us achieve a competitive advantage. "
– Jim Finnegan, Sr. Vice President of Silicon Engineering, Netronome
"We’ve determined that 90% of the risk is in chip interfaces. If we design the interfaces incorrectly, it doesn’t matter if we get the rest of the chip right. This is especially true with PCI Express since it’s such a complex protocol. The bottom line for us is that the choice we made to go with proven IP that’s easy to get up and running is really just good, solid common sense."
– Jim O’Connor, Vice President of Engineering, iVivity
"We work to ensure our customers have access to best-in-class products in our ecosystem, such as Denali’s PureSpec verification IP (now Cadence VIP Catalog), a high-quality comprehensive verification IP solution. The collaboration between IBM and Cadence gives designers the ability to quickly implement customized Power Architecture-based applications in world-leading semiconductor technologies."
– Jim Cuffney, Executive Project Mgr, PowerPC Cores Development, IBM Microelectronics
"M-PCIe helps boost mobile device performance by delivering best-in-class, highly scalable I/O functionality, enabling the migration of business apps to smartphones and tablets as they take on the role of primary computing devices. We are delighted that Cadence is enabling SoC developers to rapidly adopt M-PCIe by delivering IP and VIP products supporting this standard."
– Al Yanes, Chairman and President, PCI-SIG
“As the complexity of ARM partners’ designs increases year after year, successfully verifying the performance of the SoCs has become a critical imperative. The comprehensive Cadence Verification IP solution for AMBA® protocols has enabled our mutual customers to address this challenge while incorporating the latest ARM technology. The ARM partnership with Cadence helps customers achieve continued success as they roll out next-generation designs incorporating our most advanced AMBA specifications such as AXI4 and AXI Coherency Extensions (ACE™).”
– Joe Convey, Director of Design Enablement, ARM
"Mobile device users demand ever-increasing power efficiency, and the MIPI Alliance chip-to-chip interfaces are an essential low-power technology for smartphone and tablet developers. As an early contributing member of the MIPI Alliance, Cadence has helped speed the adoption of mobile specifications, now including the M-PHY-based M-PCIe."
– Joel Huloux, Chairman of the Board, MIPI Alliance
“As Cadence promised, our validation environment now runs hundreds of times faster than with simulation. Accelerated VIP running on the Palladium® XP (platform) increased my team’s productivity by 100%. It also enabled us to find bugs we were unable to reach using simulation.”
– Tony Gladvin George, Verification Engineer, Samsung
The S.M.A.R.T. Choice
Cadence VIP is the smart choice for your next project. Customers continue to choose Cadence VIP for the unique benefits it delivers, including:
SoC-level verification power
- Boost simulation performance by 100 times and more using Accelerated VIP with the Palladium XP series of hardware accelerators
- Verify conformance with SoC interconnect IP rules using Interconnect Validator
- Enable SoC latency and bandwidth analysis with Interconnect Workbench
- Verify all your memory interfaces with Memory Models spanning:
- 6000 memory components
- 60 types of memory interfaces
- 85 memory manufacturers
Availability of protocols
- Verify all the complex interfaces in your design with interface VIP covering more than:
- 40 communication protocols
- 60 memory interfaces
- Leverage the outstanding Cadence track record of being first to market with support for new protocols
Ready-made for your environment
- Maximize the value of your simulation licenses and get consistent results whether you use the Cadence Incisive®, Synopsys VCS, or Mentor Questa simulators
- Use the verification language that you prefer. Choose from SystemVerilog, e, Verilog, VHDL, or C/C++
- Migrate to the Universal Verification Methodology (UVM) or continue using the legacy methodologies that preceded it. It's your choice!
Technically advanced features
- Perform superior protocol compliance verification with TripleCheck IP Validator
- Shorten time-to-first test with the PureView graphical configuration utility
- Use available Assertion-Based VIP for exhaustive formal verification of parallel bus protocols
Why is VIP Important?
The SoC development process typically requires months of digital simulation effort to verify the functional performance of an SoC before taping out the design. In fact, simulation will usually continue after tapeout and until the time that silicon is received back from the lab. The reason for this extended effort is that functional verification is never finished! SoCs are simply too complex for the logical design to ever be 100% verified. Recognizing that verification is never finished, leading SoC developers make every effort to improve the efficiency of the verification process to complete more verification cycles before taping out a chip.
The benefit of VIP
One of the most time-consuming aspects of SoC verification is creating a testbench that models the SoC's interfaces. Since a typical SoC contains dozens of interfaces such as DDR, USB, and PCI Express, modeling all those interfaces is extremely time-consuming. VIP provides a huge benefit by modeling all those interfaces as components that can be plugged into an SoC testbench and simulated along with the chip.
The use of VIP not only saves man-months of development time, it also frees up valuable talent. SoC interface protocols can be very complex, with specifications that are hundreds of pages long. There are usually very few protocol experts in a company. Using off-the-shelf VIP frees up those valuable resources for other work. Cadence VIP helps you benefit from the experience of others. It incorporates lessons learned from a wide range of projects across many different design applications.