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Xtensa Reference Cores

Choosing the Ideal Processor for Your Next SOC Design

Today's complex consumer electronics systems include numerous deeply embedded control tasks in the dataplane far removed from the main system CPU. For example, today's advanced smartphone design can include as many as 20 deeply embedded controllers running protocol stacks for WiFi, Bluetooth, NFC, LTE, and 3G interfaces; handing complex video and imaging tasks; managing security; and more.

The Cadence® Tensilica® DPUs excel at deeply embedded control and data tasks. We created a family of Xtensa® Reference Cores to showcase representative processors that make it easy to choose one that is closest to what is needed out of the whole possible range.

So whether you want to use one of the cores as-is, or build your own task-optimized processor in a matter of minutes by tweaking it, we offer an easy path to the right processor for your design.

The reference controllers cover a range of use cases from a tiny cacheless microcontroller to a high-performance 4-issue real-time controller.

Xtensa processor templates as starting points for the ideal processor for each task

Starting Points for Your Next Design

Choose from three reference controllers as starting points:

  • XRC-5C2—A small general purpose microcontroller
  • XRC-5C4—A general purpose, efficient, real-time embedded processor
  • XRC-5C6—A general purpose, high performance real-time embedded processor

Feature Comparison of Xtensa Reference Cores

Which Reference Core is the Right Starting Point for Your Application?

Xtensa Reference Cores cover the broadest range of performance of any embedded computing architecture and form the starting points for creating the ideal processor for your application. Here is a feature chart to help you figure out which is closest to what you need.

Reference Core Selector Guide

Pipeline stages 5 5 5
Instruction width (bits) 16/24/32 16/24/64 16/24/96
Multiple instruction issue (static superscalar) Up to 2 Up to 3 Up to 4
Local memory data path width (bits) 32 32 32
General-purpose registers 16 32 64
Instruction cache size N/A 32Kb 32Kb
I-Cache associativity N/A 2-way 2-way
Data cache size N/A 32Kb 32Kb
D-Cache associativity N/A 2-way 2-way
Local instruction RAM, user selectable size, maximum size 128Kb N/A N/A
Local data RAM, user selectable size, maximum size 128Kb N/A N/A
System interface width 32 32 32
Load / Store units 1 1 2
MUL 16 yes yes yes
MAC 16-bit single cycle no yes yes
32x32 MUL32 yes yes yes
Divider (32bit integer) no no yes
Sign Extend, NSA, MIN/MAX, DEPBITS no yes yes
Zero-overhead looping no yes yes
Interrupts 2 2 2
On-chip debug (OCD) no (optional) no (optional) no (optional)


Additional Benefits

Based on the Proven Xtensa Architecture

All reference cores are based on the Xtensa Instruction Set Architecture (ISA), a 32-bit RISC architecture with a 32-bit ALU; 16, 32 or 64 general-purpose registers; six special purpose registers; and 80 base instructions. The Xtensa ISA employs 24-bit instructions with 16-bit narrow encodings for the most common instructions. These 16- and 24-bit instruction words are freely intermixed to achieve higher code density without compromising application performance. These templates use FLIX (VLIW), when efficient, where these 2- to 4-issue instructions are modelessly intermixed with 16- and 24-bit instructions.

Rich Controller Features Set

All reference cores have minimal number of interrupts that can be increased if needed. Nine external interrupts at different hardware-defined priority levels are available to provide system flexibility. Additionally, three timer interrupts and two software interrupts are available. For extreme time-critical applications, a non-maskable interrupt is included.

Ideal in Low-Power Applications

We use clock gating, data gating and other architectural enhancements to keep power as low as possible. Clock and data gating stops unnecessary clocking activity to parts of the processor that are not in use on a particular clock cycle.

Support for Power Shut-Off (PSO) allows parts of the processor to be turned off when not being used to reduce leakage power.

The Loop Buffer allows the processor to run out of a small, low power instruction store rather than accessing the higher power local cache when running tight loops.

System bus

Capable of receiving inbound requests from an external master such as DMA with sophisticated system bus features such as split-transactions and multiple outstanding requests are also supported.

You have three system bus choices:

  1. No System bus—For deeply embedded, low cost designs
  2. ARM® AMBA® 2.0 AHB-Lite—For fast integration into AMBA-based designs
  3. AMBA 4.0 AXI bus bridge—For fast integration into AMBA-based designs

Build Your Own—Customize Your Processor

Like The Xtensa Reference Cores, But Want More?

Our reference cores are regular Xtensa processors that have been pre-configured. Many of our customers are not satisfied with just these options—they are close to what they need, but some want just a little bit more (or a little bit less). That's the beauty of our system.

You can start with a reference core and add what you want, or take away what you don't want, using our Xtensa processor development tools. Many options are simple click-box choices.

If you're not sure, just play around and see how little changes affect your software profile.

Check out our Xtensa processor section to see the wide set of options that are available to you right now.

Comprehensive Hardware and Software Design Tools

Our Proven, Comprehensive Hardware and Software Design Environment

DPU design process


For Processor Designers

Cadence delivers patented, proven tools that automate the process of generating a custom DPU along with matching software tools. These tools have been proven in hundreds of designs. Whether your design is for a simple controller or a complex multi-core DSP design, Cadence has the tools you need to create successful products.

View the complete set of  tools for processor designers.

Software development process

For Software Developers

When you need to develop application code for a Tensilica DPU, the Xtensa Software Developer's Toolkit provides a comprehensive collection of code generation and analysis tools that speed the development process. Cadence's Eclipse-based Xtensa Xplorer Integrated Development Environment (IDE) serves as the cockpit for the entire development experience.

View the complete set of  tools for software developers.