The Cadence Tensilica Vision DSP

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Tensilica Vision DSPs for Imaging and Computer Vision

Built for Next-Generation Imaging/Vision Requirements

IP for next generation image/video processing

Today’s applications processors are not equipped to handle the complex vision/imaging digital signal processing (DSP) functions in mobile handsets, tablets, DTVs, drone and automotive, video game, and high end wearable. The Cadence® Tensilica® Vision P5 is a fourth generation DSP, offering a much-needed breakthrough in terms of energy efficiency and performance that enables applications never before possible in a programmable device.

The Tensilica Vision P5 DSP was designed for the complex algorithms in imaging and computer vision including innovative multi-frame noise reduction, video stabilization, high dynamic range (HDR) processing, object and face recognition, and tracking, low-light image enhancement, digital zoom, gesture recognition plus many more.

Our Tensilica Vision P5 DSP offers up to 4X-100X the performance relative to traditional mobile CPU+GPU systems at a fraction of the power/energy.

Samsung and LG are using Cadence's Tensilica HiFi Audio in their DTVs.

Offload the Host CPU for Intensive Imaging and Vision Apps

The Tensilica Vision P5 DSP offloads the host CPU for lower energy consumption running intensive imaging and vision apps. Multi-core host CPUs can’t handle these power-hungry, bandwidth-demanding applications, hardwired accelerators are restricted to a fixed set of functions, and GPUs offer pipelines that are not required or not efficient in image and video processing applications. 

Now, the Tensilica Vision P5 DSP provides an imaging-specific programmable solution that is an ideal complement to the CPU/GPU. Imaging and vision algorithms can run on a DSP that’s specifically optimized for the imaging and vision functions required.

Image and Computer Vision Processing

Programmable and Customizable

The Tensilica® Vision P5 DSP is a synthesizable processor, with the configurability and extensibility that users have come to value from Cadence. The instruction set, memory system, and data types have all been optimized for high-throughput 8-, 16-, and 32-bit pixel processing. 

Highly Energy Efficient

The Vision P5 DSP is highly energy efficient compared to CPUs or GPUs for all kinds of pixel operations.

High Performance

The Vision P5 DSP offers a 5-way VLIW architecture, where each VLIW slot can perform 64-way SIMD 8 bit operations. The DSP is designed to provide 320 operations per clock cycle.

That's up to 13x performance improvement over its predecessor, the IVP-EP DSP.

The Vision P5 DSP can achieve even higher efficiency with its wide SIMD multiply-accumulates, offering significantly enhanced performance for the pixel filtering and image analysis features common in computer vision applications.


The Vision P5 DSP Architecture

Vision P5 DSP for Fixed-Point Vision/Imaging

The Tensilica Vision P5 DSP is available as licensable, synthesizable IP with rich software tools and libraries. The instruction set, memory system, and data types have all been optimized for high-throughput 8-, 16-, and 32-bit pixel processing. The Vision P5 DSP was also architected to be used in solutions requiring multiple Vision P5 DSPs to provide higher performance if required.

Wide Vector SIMD Data Processing for Superior Performance

The VLIW issue of vector operations gives an almost arbitrary mix of loads, stores, multiplies, and ALU operations, resulting in a rich set of pixel computations. Up to 320 operations can be issued per cycle and 256 of these can be ALU operations.


The Vision P5 DSP also integrates a highly sophisticated SuperGather™ unit which provides the ability to quickly and efficiently read/write from non-contiguous local memory locations. The SuperGather unit enables the full utilization of the available SIMD capabilities for algorithms such as warping, lens distortion correction and canny edge tracing.

Imaging Instructions

The Tensilica Vision P5 DSP includes many imaging-specific operations that accelerate 8-, 16-, and 32-pixel data types and video operation patterns. Some examples of these instructions are arithmetic operations (ADD, SUB, COMPARE, MUL, DIVIDE), bit manipulation operations, and data reorganization operations. 

Vector Floating Point

The Vision P5 DSP also provides an optional vector floating point unit for those applications which need that acceleration. The Vector floating point offers significant performance improvement with a very little area increase.

Processor Optimization

Because the Vision P5 DSP is built on our proven Tensilica Optimization Platform, further optimizations can be made to target your specific application. Please see the Xtensa section for all of the options available. All processors come with a complete hardware design with matching software tools, including a mature, world-class auto-vectorizing compiler, a cycle-accurate SystemC-compatible instruction set simulator (ISS) and the full industry standard GNU toolchain. 

Support for IVP-EP DSP

Yes. Cadence still supports our popular IVP-EP imaging DSP. As a matter of fact, it might be a better solution for you than the Tensilica Vision P5 DSP, depending on your requirements.  Be sure to check with your Cadence field application engineer, who can help you make the best choice.

The IVP-EP DSP is a licensable, synthesizable processor with an instruction set, memory system, and data types optimized for high-throughput fixed-point 8-, 16-, and 32-pixel processing. The VLIW issue of vector operations gives an almost arbitrary mix of loads, stores, multiplies, and multiple ALU operations, thereby offering a rich set of pixel computations. The VLIW and wide SIMD architecture enables massively parallel processing.

The architecture can scale by both the number of element engines and the number of processors.

Library and Third-Party Support

OpenCV/VX Library Support

The Tensilica Vision P5 DSP comes with over 800 OpenCV functions. These functions are highly optimized to achieve the best performance on this DSP. OpenCV has over 2500 functions but Cadence has chosen the most common 800 functions to optimize. Cadence continues to add more functions with quarterly library updates.

OpenVX has ~40 library functions. All of these functions are already available on the Vision P5 DSP.

Rich Third-Party Application Software Support

Along with math library support Cadence also supports a very rich set of third party applications targeting the IVP-EP and Vision P5 DSPs. Some of these third parties offer video WDR, image stabilization, super resolution, and various ADAS applications. These applications are ported and optimized on our DSPs for fast time to market. 

See our list on our Partners page.

Comprehensive Hardware and Software Design Tools

Our Proven, Comprehensive Hardware and Software Design Environment

Processor design process


For Processor Designers

Cadence delivers patented, proven tools that automate the process of generating a custom processor or DSP along with matching software tools. These tools have been proven in hundreds of designs. Whether your design is for a simple controller or a complex multi-core DSP design, Cadence has the tools you need to create successful products.

View the complete set of tools for processor designers.

Software development process

For Software Developers

When you need to develop application code for a Tensilica processor, the Xtensa Software Developer's Toolkit provides a comprehensive collection of code generation and analysis tools that speed the development process. Cadence's Eclipse-based Xtensa Xplorer Integrated Development Environment (IDE) serves as the cockpit for the entire development experience.

View the complete set of tools for software developers.

FPGA Platform

Cadence has developed a complete camera system, display system and Vision P5 DSP on a FPGA platform. The FPGA platform can be used to develop various vision and imaging applications. It has a CMOS sensor based camera connected over a MIPI interface and an LCD panel connected over another MIPI interface. It also has an HDMI input and output which provides a highly flexible platform for developing imaging and vision applications. Cadence has already developed various applications including face detection and people detection on this FPGA platform.

Vision Demo System

Vision P5 Literature and Other Resources

Documentation and Literature

Product Literature

Vision P5 DSP Product Brief

IVP-EP DSP Product Brief

White Paper

Choosing the Right DSP for High-Resolution Imaging in Mobile and Wearable Applications

Please contact us for datasheets and more relevant documentation.

Hardware/Software Design Tools

Xtensa Processor Developer's Toolkit
Xtensa Software Developer's Toolkit

Read Blog on Vision P5

 Q&A: Drones, Robots, and the New Tensilica Imaging/Vision DSP

Watch Videos on IVP