The IVP Image/Video DSP

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Image/Video Processing

Built for Next-Generation Imaging/Video Requirements

IP for next generation image/video processing

Today's applications processors are not equipped to handle the complex image/video signal processing functions in mobile handsets, tablets, DTVs, and automotive, video game, and computer vision applications.

The Cadence® imaging product line offers a much-needed breakthrough in terms of energy efficiency and performance, enabling applications never-before possible in a programmable device.

The IVP DSP family was designed for the complex algorithms in imaging, video, and computer vision including innovative multi-frame image capture and video pre- and post-processing, video stabilization, HDR image and video processing, object and face recognition, and tracking, low-light image enhancement, digital zoom, and gesture recognition.

And our newly announced IVP-EP DSP now offers up to 4X the performance relative to the IVP DSP.

Offload the Host CPU for Intensive Imaging and Video Apps

Even multi-core host CPUs just can’t handle these demanding applications.The power required to run high-resolution video processing eats up battery life and slows other applications.

Some of these functions have been offloaded to hardwired accelerators. However, these fixed-hardware implementations are virtually impossible to program and are therefore restricted to a fixed set of functions. When new, enhanced algorithms are developed, these hardware blocks need to be redesigned. And the number of hardware blocks for all of the possible image and video enhancement algorithms just keeps growing.

GPUs, possible alternatives, typically offer floating point pipelines designed specifically for 3D graphics algorithms that are mostly not required or efficient in image and video processing applications.

This opens up an opportunity for a imaging-specific programmable solution that is a good complementary engine alongside the CPU.  Now imaging and video algorithms can run on a processor-based DSP that’s specifically optimized for the pixel computations required.

Watch Videos on IVP

A Complete Platform for Image and Video Processing

A Complete Platform for Image and Video Processing

The IVP and IVP-EP are licensable, synthesizable processors, with configurability and extensibility that users have come to know from the Cadence Tensilica IP products.  The instruction set, memory system, and data types have all been optimized for high-throughput 8-, 16-, and 32-bit pixel processing. 

IVP Subsystem 

The IVP Platform

Highly Energy Efficient

The IVP and IVP-EP are highly energy efficient compared to CPUs or GPUs for all kinds of pixel operations (e.g., absolute-difference, multiply-add, shift-saturate). As an example, for IVP implemented in an automatic synthesis, place-and-route flow in 28nm HPM process, regular Vt, a 32-bit integral image computation on 16b pixel data at 1080p30 consumes 10.8mW. The integral image function is commonly used in applications such as face and object detection and gesture recognition.

High Performance

IVP and IVP-EP demonstrate high performance on complex kernels such as motion search and normalized cross-correlation, commonly used in high-precision block and feature matching and optical flow. For a smart motion search on 16-bit data over a 1920x1080 frame with 256x16 pixel search range and 9x3 pixel block size, IVP can achieve a rate of 142 sums of absolute differences per cycle. a normalized cross-correlation function on 16-bit pixel data with 32-bit accuracy achieves 1 million 8x8 blocks per second.

IVP-EP can achieve even higher efficiency with its wide SIMD multiply-accumulates, offering significantly enhanced performance for pixel filtering and image analysis features common in computer vision applications.

The IVP and IVP-EP Imaging/Video Core Architecture

SIMD/VLIW Fixed-Point Imaging/Video DSPs

The IVP and IVP-EP are licensable, synthesizable processors with rich software tools and libraries. The instruction set, memory system, and data types have all been optimized for high-throughput 8-, 16-, and 32-bit pixel processing. They have an architecture that can scale by both the number of element engines as well as the number of processors.

Details on the Core Architecture

VLIW, Widest Vector SIMD Data Processing for Superior Performance

The VLIW issue of vector operations gives an almost arbitrary mix of loads, stores, multiplies, and multiple ALU operations; and the architecture offers a rich set of pixel computations.  VLIW and wide SIMD enables more parallel processing than other DSPs on the market today.

Custom Instructions

The IVP and IVP-EP features many imaging-specific operations to accelerate 8-, 16-, and 32-pixel data types and video operation patterns.

Highly Customizable Processor

Because the IVP family is based on our proven Xtensa architecture, the core can be further optimized and configured using our automated Tensilica processor generator system. Please see the Xtensa section for all of the options available. The Xtensa Processor Generator creates a complete hardware design with matching software tools, including a mature, world-class auto-vectorizing compiler, a cycle-accurate SystemC-compatible instruction set simulator (ISS) and the full industry standard GNU toolchain.

Comprehensive Hardware and Software Design Tools

Our Proven, Comprehensive Hardware and Software Design Environment

DPU design process

 

For Processor Designers

Cadence delivers patented, proven tools that automate the process of generating a custom DPU along with matching software tools. These tools have been proven in hundreds of designs. Whether your design is for a simple controller or a complex multi-core DSP design, Cadence has the tools you need to create successful products.

View the complete set of tools for processor designers.

Software development process

For Software Developers

When you need to develop application code for a Tensilica DPU, the Xtensa Software Developer's Toolkit provides a comprehensive collection of code generation and analysis tools that speed the development process. Cadence's Eclipse-based Xtensa Xplorer Integrated Development Environment (IDE) serves as the cockpit for the entire development experience.

View the complete set of tools for software developers.

IVP Literature and Other Resources

Learn More About IVP Imaging/Video DSPs

 

May 2014 Embedded Vision Summit Presentation: Tensilica

Chris Rowen, Fellow at Cadence, presents the "Taming the Beast: Performance and Energy Optimization Across Embedded Feature Detection and Tracking" tutorial at the May 2014 Embedded Vision Summit West.May 2014 Embedded Vision Summit Technical Presentation: Tensilica

This video is © 2014 Embedded Vision Alliance and is used with permission. For more embedded vision information, please visit www.embedded-vision.com.

 

April 2013 Embedded Vision Summit Presentation: Tensilica

Chris Rowen, Chief Technology Officer at Tensilica, presents the "Porting Applications to High-Performance Imaging DSPs" tutorial within the "Developing Vision Software, Accelerators, and Systems" technical session at the April 2013 Embedded Vision Summit.

This preview video is © 2013 Embedded Vision Alliance and is used with permission. For the full version of the video, please click here to visit the Embedded Vision Alliance website. One-time registration and login are required prior to accessing the video.

Documentation and Literature

Product Literature

Image/Video DSP Cores Datasheet

Please contact us for datasheets and more relevant documentation.

Hardware/Software Design Tools

Xtensa Processor Developer's Toolkit
Xtensa Software Developer's Toolkit