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Xtensa Processor Templates

Choosing the Ideal Processor for Your Next SOC Design

Today's complex consumer electronics systems include numerous deeply embedded control tasks in the dataplane far removed from the main system CPU. For example, today's advanced smartphone design can include as many as 20 deeply embedded controllers running protocol stacks for WiFi, Bluetooth, NFC, LTE, and 3G interfaces; handing complex video and imaging tasks; managing security; and more.

The Cadence® Tensilica® DPUs excel at deeply embedded control and data tasks. We created a family of Xtensa® processor templates to showcase representative configurations that make it easy to choose one that is closest to what is needed.

So whether you want to use one of the processor template as-is, or build your own task-optimized processor in a matter of minutes by tweaking a template, we offer an easy path to the right processor for your design.

The processor templates cover a broad spectrum of use cases ranging from a tiny cacheless controller to a high-performance 3-issue VLIW DPU.

Xtensa processor templates as starting points for the ideal processor for each task

Five Starting Points for Your Next Design

We've created five processor templates as starting points:

  • 106Micro—A small cache-less controller
  • 108Mini—A mid-sized, cache-less controller with DSP instructions
  • 212GP—Our mid-range controller with caches and DSP instructions
  • 233L—Our mid-range controller for Linux
  • 570T—A high-performance 3-issue VLIW DPU for real-time applications

Feature Comparison of Xtensa Processor Templates

Which Processor Template is the Right Starting Point for Your Application?

Xtensa processor templates cover the broadest range of performance of any embedded computing architecture and form the starting points for creating the ideal processor for your application. Here is a feature chart to help you figure out which template is closest to what you need.

Template Selector Guide

Pipeline stages 5 5 5 5 5
Instruction width (bits) 16/24 16/24 16/24 16/24 16/24/64
Multiple instruction issue (static superscalar) no no no no 3 issue or 2 issue
Local memory data path width (bits) 32 32 32 32 64
General-purpose registers 32 32 32 32 32
Instruction cache size N/A N/A 8Kb 16Kb 16Kb
I-Cache associativity N/A N/A 2-way 4-way 2-way
Data cache size N/A N/A 8Kb 16Kb 16Kb
D-Cache associativity N/A N/A 2-way 4-way 2-way
Local instruction RAM, user selectable size, maximum size 128Kb 128Kb 128Kb N/A 128Kb
Local data RAM, user selectable size, maximum size 128Kb 128Kb (dual) 128Kb N/A 128Kb
XLMI Interface no no yes no yes
Input/output ports (32 bits wide) no yes yes yes yes
Input/output queues (32 bits wide) no no no no yes
System interface (PIF) width 32 32 32 32 64
MUL 16 yes yes yes yes yes
MAC 16-bit single cycle no no yes yes yes
32x32 MUL32 yes yes yes yes dual
32-bit integer divide no yes yes yes yes
Sign Extend, NSA, MIN/MAX yes yes yes yes yes
Zero-overhead looping no no yes yes yes
External interrupts 12 16 16 16 16
Timer interrupts 1 3 3 3 3
Software interrupts 1 2 2 2 2
Non-maskable interrupt yes yes yes yes yes
On-chip debug (OCD) yes yes yes yes yes


Additional Benefits

Based on the Proven Xtensa Architecture

All processor templates are based on the Xtensa Instruction Set Architecture (ISA), a 32-bit RISC architecture with a 32-bit ALU; 16, 32 or 64 general-purpose registers; six special purpose registers; and 80 base instructions. The Xtensa ISA employs 24-bit instructions with 16-bit narrow encodings for the most common instructions. These 16- and 24-bit instruction words are freely intermixed to achieve higher code density without compromising application performance. On some processors, 64-bit VLIW is utilized when efficient, and these 2- or 3-issue instructions are modelessly intermixed with 16- and 24-bit instructions.

Rich Controller Features Set

All processor templates use a rich interrupt architecture. Nine external interrupts at different hardware-defined priority levels provide system flexibility. Additionally, three timer interrupts and two software interrupts are available. For extreme time-critical applications, a non-maskable interrupt is included.

Ideal in Low-Power Applications

We use clock gating and other architectural enhancements to keep power as low as possible. Clock gating stops unnecessary clocking activity to parts of the processor that are not in use on a particular clock cycle.

Bypass the Bus for High-Speed I/O

Most of our processor templates come with innovative ways to bypass the system bus for the fastest possible I/O.

  1. GPIO ports—Wires directly connect the processor to another processor or external RTL. There are two 32-bit GPIOs bundles for two-way high-speed communication, making them ideal to quickly set control bits for the rest of the system as well as read system status information.
  2. Queue interfaces—FIFO queues provide a high-speed mechanism to transfer streaming data. The data is always available without the need to load or store the data before or after computation.

For example, the 570T processor template includes both GPIO ports and queues. In the example below, it is used to decode MP3 audio:

Direct Interfaces

The GPIO ports exchange control signals with the I2S interface logic. The FIFO queue sends the decoded audio stream to the DAC via the i2S interface logic, totally bypassing the bus for high-speed audio.

Optional AMBA Bridges

You have three integration choices:

  1. Our PIF—An advanced, high-performance system bus that services all external memories and peripheral devices in a typical Cadence-based system. The PIF is capable of receiving inbound requests from an external master such as DMA. Sophisticated system bus features such as split-transactions and multiple outstanding requests are also defined by the PIF protocol
  2. ARM® AMBA® 2.0 AHB-Lite bridge—Converts all signals between the AMBA and PIF protocols. All processor templates include pre-configured Verilog for the bridge for fast integration into AMBA-based designs
  3. AMBA 3.0 AXI bus bridge—Enables very simple hardware integration of the processor into an AMBA 3.0-based system

Build Your Own—Customize Your Processor

Like The Xtensa Processor Templates, But Want More?

Our processor templates are regular Xtensa processors with pre-configured options that many people like. Many of our customers are not satisfied with just these options—they are close to what they need, but some want just a little bit more (or a little bit less). That's the beauty of our system.

You can start with a processor template and add what you want, or take away what you don't want, using our Xtensa processor development tools. Many options are simple click-box choices.

If you're not sure, just play around and see what the effects of little changes make on your software profile.

Check out our Xtensa processor section to see the wide set of options that are available to you.

Comprehensive Hardware and Software Design Tools

Our Proven, Comprehensive Hardware and Software Design Environment

DPU design process


For Processor Designers

Cadence delivers patented, proven tools that automate the process of generating a custom DPU along with matching software tools. These tools have been proven in hundreds of designs. Whether your design is for a simple controller or a complex multi-core DSP design, Cadence has the tools you need to create successful products.

View the complete set of tools for processor designers.

Software development process

For Software Developers

When you need to develop application code for a Tensilica DPU, the Xtensa Software Developer's Toolkit provides a comprehensive collection of code generation and analysis tools that speed the development process. Cadence's Eclipse-based Xtensa Xplorer Integrated Development Environment (IDE) serves as the cockpit for the entire development experience.

View the complete set of tools for software developers.