DSPs for Baseband and RF Signal Processing | Cadence IP

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DSPs for Baseband and Communications

Tackling the hard data processing tasks

Baseband and RF Signal Processing IP

Cadence offers more ways to perform complex signal processing than any other IP company. Cadence offers a full range of processors and DSPs for the best combination of high performance, low power, and small area, exactly tailored to your application.

From the dual or quad MAC Fusion F1 up to the super-high-performance 64-MAC ConnX BBE64EP, these Tensilica DSPs are designed for a broad range of communications applications. Go with the industry's best performing and most compact low-power DSPs for applications from Bluetooth, SmartGrid, 802.11 modems, up to 4G LTE-Advanced and 5G. Cadence offers several pre-designed, pre-verified DSP processors so you can accelerate your design effort and shorten your time to market.

No matter which Tensilica processor solution you choose, remember that it's based on our 32-bit Xtensa® RISC processor and toolset. Unlike a traditional fixed-configuration DSP, all Tensilica DSPs and processors are fully:

  • Configurable—Select the pre-built functions you need with full C language, library, and verification support.
  • Extensible—Add custom instructions using our Verilog-like TIE language. The results are automatically integrated into the programming tools with full verification support. Custom ports allow your hardware accelerators to be directly integrated into the core, appearing to the programmer as a standard instruction.
  • Scalable—Configurable I/O ports and memory allow you to easily scale your performance from a simple single-core design to a sophisticated direct ported multi-core solution.

Whether your need is for a single DSP, a homogeneous multi-core solution, or a highly optimized heterogeneous mix of processors, DSPs, and hardware accelerator blocks, our family of communications DSPs, is the ideal place to get started on your communications platform design.

Tensilica Fusion F1 DSP for Communications and IoT The Tensilica Fusion F1 DSP is flexible for IoT, Wearables and Wireless Connectivity

Flexible Fusion F1 architecture for narrowband Wireless and IoT

No one processor can meet the varied demands of IoT, wearables, and wireless communications. That's why we developed the Cadence® Tensilica® Fusion F1 DSP, with the flexible options you need to mold the DSP into just what you need. 

This scalable DSP is ideal for applications requiring merged controller plus DSP computation, ultra-low energy and a small footprint. It can be designed into SoCs for wearable activity monitoring, indoor navigation, context-aware sensor fusion, secure local wireless connectivity, face trigger, voice trigger and voice recognition. Optional Instruction Set Architecture (ISA) extensions are included to accelerate multiple wireless protocols. The Fusion F1 DSP ISA also includes some Viterbi acceleration instructions, to speed up communication protocols using Viterbi algorithms.  

A configurable approach to meet your needs

The Tensilica Fusion F1 DSP combines an enhanced 32-bit Xtensa® control processor with market-leading DSP features and flexible algorithm-specific acceleration for a fully programmable approach, supporting multiple existing and developing standards as well as customer algorithms. For many IoT applications that are space- and energy-constrained, deploying a single, small, low-energy processor that can perform all of the programmable functions (sensor processing, wireless communications and control) is ideal. IoT device designers can pick just the options they need using the Xtensa Processor Generator to produce a Tensilica Fusion F1 processor that can be smaller and more energy-efficient than a single one-size-fits-all processor while still having higher performance. 

A proven base architecture with lots of flexibility

The Tensilica Fusion F1 DSP offers low energy, high performance control and signal processing for a broad segment of IoT/wearable markets. This highly configurable architecture is specifically designed to excel at always-on processing - including wake-on-voice and sensor fusion applications - that require a merged controller plus DSP, ultra-low energy, and a small footprint. It can be designed into SoCs for wearable activity monitoring, indoor navigation, context-aware sensor fusion, face trigger, voice trigger, and voice recognition.

Additionally, the Tensilica Fusion F1 DSP is very efficient in running the narrowband wireless communications standards typically associated with IoT device communications, including protocols such as Bluetooth Low Energy, Thread and Zigbee using IEEE 802.15.4, SmartGrid 802.15.4g, Wi-Fi 802.11n and 802.11ah, 2G and LTE Category 0 release 12 and 13, and global navigation satellite systems (GNSS).

TENSILICA FUSION F1 BASE ARCHITECTURE
Feature Supported Benefits
VLIW Slots 2 Allows two concurrent operations
Fixed-point MACs per Cycle One 32x32
Two 24x24
Two 16x16 (four optional)
Flexible MAC architecture efficiently handles broad set of data types
Accumulator 64-bit
ITU/ETSI Intrinsics Yes Accelerates ITU/ETSI voice codec performance
Circular Buffer Yes Efficiently manage streams of data
Customer-defined Instructions for Further Optimization Yes Extend the ISA to efficiently meet customer requirements
Prefetch for Cache-based Configurations Optional Improves cache memory performance

DSP plus control

All Tensilica Fusion F1 DSPs are click-box additions to our customizable Xtensa® processor and include the base Xtensa instruction set. In other words, they are excellent targets for control applications as well.

Customizable to meet your requirements

Because our Tensilica Fusion F1 DSPs are based on our Xtensa processor, you get all of the customization advantages that our processors are known for, along with incredible flexibility, including (but not limited to):

  • Add/configure caches and local memories
  • Add direct RTL-like interfaces via Ports, Queues, and Lookup Interfaces
  • Add custom instructions with full compiler support

See our Xtensa product section for more details.

Optimized for always-on voice trigger and recognition

The Tensilica Fusion F1 DSP is our smallest, lowest power DSP supporting always-listening voice trigger and speech command modes. It enables a hands-free experience. Cadence is working with several software partners who provide innovative voice activation, speech command recognition, voice pre-processing and noise reduction products—all optimized on the Tensilica Fusion F1 DSP.

Fully programmable in C

The Tensilica Fusion F1 DSP is fully programmable in C, with no assembly required. So if you have proprietary algorithms to port, it’s easy and quick.

The features you need for applications ranging from ultra-low energy to high performance

Choosing a processor for IoT/wearable applications is a challenge. No one processor will be optimal for all IoT applications – one size does not fit all. In choosing a processor, it is desirable to have high configurability to scale the breadth of potential applications. It is also highly desirable that this processor architecture has very good DSP performance, both fixed and floating point, to process all of the sensor data available in these new devices. Finally, IoT/wearable processors need to be very energy efficient as many applications will be powered by small batteries, or rely on energy harvesting.

The Tensilica Fusion F1 DSP is based on the proven Xtensa Innovation Platform, which means it is highly configurable and you can add custom I/O and instructions to fit the needs of your application. In addition to the standard Xtensa processor configuration options, we've developed five optional blocks, tightly integrated with the main processor, to accelerate your design effort and help you customize the processor for your unique requirements.

Tensilica Fusion F1 IoT options

These five proven Tensilica Fusion F1 options for IoT applications include:

TENSILICA FUSION F1 OPTIONS
Option Benefits
Floating Point Unit
  • Single-precision
  • Floating point instructions issued concurrently with 64-bit load/store
  • Accelerates sensor processing algorithms
Audio/Voice/Speech (AVS)
  • Software compatibility with the HiFi DSP family
  • Access to over 170 HiFi audio/voice software packages
16-bit Quad MAC
  • Four 16x16 MACs
  • Accelerates communications standards like Bluetooth LE and Wi-Fi
  • Accelerates voice algorithm performance
AES (128 bit)
  • Encryption acceleration for narrowband wireless standards such as Bluetooth LE and Wi-Fi
Advanced Bit Manipulation
  • Accelerates performance of bit operations in baseband MAC/PHY processing

A strong partner ecosystem

Cadence has over 70 partners in its comprehensive ecosystem.. See the list on our Partners page. These companies, ranging from industry giants like Dolby and DTS to innovative companies for sensor fusion, always-on, sound enhancement, and noise reduction, have already ported their software to the Tensilica Fusion F1 DSP architecture so you don't have to. Get up and running very quickly with the software you need.

Learn more about Tensilica Fusion F1 DSPs

Datasheet

Fusion F1 DSP
Fusion G3 DSP

White Papers

Keeping Always-On Systems On for Low-Energy Internet-of-Things Applications
Managing Multiple Wireless Standards for Smart Home Applications
Meeting Multiple IoT Application Requirements with a Single, Configurable DSP Core

Videos

Chris Rowen highlights the requirements of the wide variety of sensors – environmental, motion, audio, and imaging. He'll cover data rates, sample rates, and levels of computation associated with sensors. He'll also discuss why, since computational requirements vary so much, a new DSP is needed. The Tensilica Fusion DSP uses a very flexible architecture that can be tailored for the computation required by whatever sensor you use.

 

Chris Rowen talks about techniques for optimizing power in sensor-based IoT devices and always-on subsystems.

 

Chris Rowen takes a look at the basic energy equation for processors and how a configurable processor architecture provides the flexibility to optimize power for a given application.

Press Release

New Tensilica Fusion DSP Sets Low-Energy Benchmarks for IoT, Wearables and Wireless Connectivity

 

ConnX BBE16EP, BBE32EP and BBE64EP DSPs for scalable baseband processing

16-, 32- and 64-MAC DSPs for demanding baseband processing

The latest additions to the product line, the Cadence Tensilica ConnX BBE16EP, BBE32EP and BBE64EP enhanced performance DSPs for baseband applications are optimized for complex number processing. The 16-MAC BBE16EP, 32-MAC BBE32EP and the 64-MAC BBE64EP offer significant improvements in maximum frequency and algorithmic performance while reducing both silicon area and power consumption versus earlier generations of DSPs. They provide unprecedented flexibility in implementing systems at power consumption levels that significantly reduce the need for hardware accelerators. With identical architectures, N-way programming model compatibility, the BBExxEP family of DSPs provide you with significant design flexibility and an easy upgrade path when needed.

The ConnX BBE EP DSPs are suitable for both infrastructure and user equipment applications. The ConnX BBE64EP is suited for multiple RF stream processing applications such as LTE-Advanced, 5G and other high-throughput MIMO systems such as 802.11ac. All of them can be easily optimized through check-box options. 

Instruction set features

  • 16-way (BBE16EP), 32-way (BBE32EP) or 64-way (BBE64EP) multiplier-accumulator (MAC), dual 8/16/32-way arithmetic logic unit (ALU) single instruction, multiple data (SIMD) engines
  • 5-issue very long instruction word (VLIW) for parallel load/store, MAC, and ALU ops
  • 32-bit scalar ALU
  • Advanced precision for matrix inversion and divide operations
  • Optimized instructions for complex arithmetic, polynomial evaluation, matrix multiplication, block floating point, bit-oriented operations, and vector compression and expansion
  • Predicated vector instructions
  • Wide memory bandwidth—128/256/512-bit load/store and 128/256/512-bit load units
  • 10-stage DSP pipeline
  • High-performance C/C++ compiler with automatic vectorization of scalar C and full support for vector data
  • TI intrinsic support, rich application libraries

The instruction set and architecture is tuned to meet the performance and computation requirements of advanced wireless systems. Compared with the typical user equipment DSP that offloads many of the computationally-intense operations to hardware acceleration blocks, ConnX BBE EP DSPs offer a more complete instruction set plus options for accelerating key algorithms while still remaining fully programmable. 

Load/store operations support five standard addressing modes and two specialized modes: bit reverse for FFTs and circular for functions like circular buffering. The addressing modes support a variety of data formats including scalar and vector, real, and complex data types.

Configurable, extensible, scalable

The ConnX BBE EP DSPs provide 13 pre-built vector options, which are included/excluded as checkboxes when defining a DSP from within the tools. These checkboxes result in seamless integration of a feature into the hardware, the compiler, the modeling tools, and the verification scripts. Using these capabilities, you can build a custom DSP without the large development schedule impact that a change in hardware design would normally involve.

Integrating an optimized FFT solution is as simple as checking a box when configuring a ConnX processor. All of the verification and tool support is provided automatically as part of the tool chain. The ConnX BBE EP DSPs can be extended to support custom ports (general-purpose wire interfaces) and queues (FIFOs) for efficient connection to offload accelerators. These custom interfaces can be defined to match the interfaces of existing third-party IP. Buffered communication between two ConnX DSPs or between a ConnX DSP and an offload accelerator can be automatically implemented using Queue interfaces and are fully supported in programming and modeling tools. These interfaces are dedicated to the offload accelerator and offer single-cycle access. Thus, ConnX BBE EP DSPs can access hardware offload accelerators in a single-cycle deterministic operation, greatly reducing power consumption and without impacting the shared system bus.

Local memories can be connected directly to a ConnX DSP, bypassing the system memory bus and allowing efficient implementation of functions that require storage of multiple intermediate datasets.

Application space—LTE, WCDMA/HSPA+, Wi-Fi, and Beyond

ConnX BBE16EP, BBE32EP and BBE64EP DSP baseband engines are high-performance DSPs designed for next-generation communication systems such as LTE Advanced, 802.11ac, and DVB. Advanced precision options are specifically designed to meet the precision and performance requirements associated with advanced MIMO systems. In addition to vector-based filtering, FFT, and matrix capabilities, a fully-featured instruction set includes a full range of bit-oriented operations used in 3G systems such as UMTS, cdma2000, and 1xEV-DO. In this way, ConnX BBE EP DSPs excel at multi-standard physical layer processing, providing opportunities for hardware savings and a broader scope of applications than a dedicated fixed-hardware solution can provide.

As physical layer (PHY) system developers move to advanced standards such as LTE-Advanced, they face the need for dramatic increases in performance from their processing platforms. ConnX DSPs meet this challenge with highly parallel vector engines. When processing needs scale beyond that of a single DSP, the ConnX BBE EP family provides smooth support for multi-core solutions. Multi-core solutions may involve other DSPs from the ConnX BBE family or extend into other Tensilica DSP processors.

System designers also face considerable uncertainty as to the algorithmic implementation that will deliver the best performance. In fact, as systems become more diverse with wide-scale deployment of heterogeneous networks, a solution that works best for a microcell operating on a bullet train in Japan may be very different from one that will work best for a similar microcell operating in a subterranean pedestrian mall in Montreal. With a fully programmable software-based solution using the ConnX BBE64EP core, you could implement both solutions on a single platform, permitting it to evolve without going back for a re-spin of silicon for new functionality or bug fixes.

The configurability and extensibility of ConnX DSPs also allows you to optimize the hardware for specific algorithms without the typical development delays associated with an ASIC design.

Using ConnX BBE16EP/32EP/64EP DSPs, you can deliver a working solution in less time than with a traditional hardware or a hybrid hardware/DSP design. You can also take advantage of the hardware platform for a broader range of applications, over a longer period of time. Ultimately, this helps reduce design time and costs, helping you to finish faster and be more competitive in the marketplace.

Supported by a complete set of hardware and software tools

Our complete set of tools includes a comprehensive instruction set simulator (ISS), which allows developers to quickly simulate and evaluate performance. The fast, functional TurboSimTM simulator option achieves speeds that are 40 to 80 times faster than the ISS for efficient software development and functional verification. System C and C-based system modeling can aid in full-chip simulations.

The tool set incudes a high-performance C/C++ compiler with automatic vectorization to support the VLIW pipeline. This comprehensive tool set also includes the linker, assembler, debugger, profiler, and graphic visualization tools. All major EDA flows are supported. See our Knowledge Center for more information on our tools and the hardware/software development process

Learn more about Tensilica ConnX DSPs

Legacy ConnX Communications DSPs

ConnX D2 - A flexible dual-MAC DSP, programmable in C

The Cadence Tensilica ConnX D2 DSP provides approximately 20% higher performance than similar dual-MAC architectures. You benefit from the flexibility of C programming with assembly-level performance.  It's an ideal solution for wireless communications, disk drives (including SSD), home entertainment devices, and computer peripherals—anything that requires a highly efficient 16-bit fixed-point DSP.

The ConnX D2 DSP adds dual 16-bit MAC units and a 40-bit register file to the base Tensilica processor. It utilizes two-way SIMD (single instruction, multiple data) instructions to provide high performance on vectorizable C code. It also delivers dual-MAC performance using 64-bit very long instruction word (VLIW) instructions for code that cannot be vectorized.

Exceptional out-of-the-box performance

The ConnX D2 DSP is tightly integrated with advanced Tensilica XCC compiler technology. The XCC compiler efficiently maps C algorithms to the ConnX D2 ISA (instruction set architecture) from native C and C intrinsic code, removing the need for time-consuming assembly code optimization. 

Consistent performance—even when vectorization is not possible

Many high-performance DSPs are large SIMD engines that run vector data through at maximum bandwidth. These DSPs rely upon compiler vectorization of C code to hit their peak performance levels.  However, if a loop isn't vectorizable, then the SIMD engine degenerates into a single-MAC DSP, and non-vectorizable code is commonplace.

By contrast, the dual MACs in ConnX D2 DSPs can be fully saturated with either SIMD instructions or VLIW instructions, delivering maximum performance on all types of C code.

Advanced DSP instruction set

The ConnX D2 instruction set is specifically optimized for the demanding numeric computations required for DSP, with 275 DSP-specific optimizing instructions. ConnX D2 DSPs efficiently perform 16-, 32-, and 40-bit fixed point additions, subtractions, and multiplies with rounding and saturation. It uses seven DSP-centric addressing schemes and adds data manipulation instructions including shifting, swapping, and logical operations to provide outstanding performance on DSP algorithms.

In addition to supporting major DSP addressing modes, ConnX D2 DSPs add specific DSP acceleration instructions such as Add-Compare-Exchange (used with Viterbi algorithms), Add Modulo, and Add Subtract. Additional instructions perform vector base loads and stores to support multiple data widths and SIMD data register loading orders, which can be aligned or unaligned.

ConnX D2 DSPs use dual-port write technology that allows two results to be written to the register files in one instruction. This can give a maximum of three writes to the register files per cycle within the VLIW implementation.

Easily further customized

Designers can further customize and optimize the ConnX D2 DSP using the flexible Xtensa Processor Generator (XPG). You can easily add multi-cycle execution units, registers, register files, and much more. You can also choose from a wide range of pre-verified configuration options.

 

ConnX BBE16 - A full-featured high-performance 16-MAC DSP, programmable in C

The ConnX BBE16 Baseband Engine combines an 8-way SIMD, 3-issue VLIW processing pipeline with a rich and extensible set of interfaces. This high-performance Cadence Tensilica DSP is built around a core vector pipeline made of 16 18bx18b MACs. These multipliers and associated adder and multiplexer trees enable operations such as FFT butterflies, parallel complex multiple operations, and signal filter structures. The results of these operations can be full precision or truncated/rounded/saturated and shifted to meet the needs of different algorithms and implementations.

The instruction set has been optimized for performance of DSP kernel operations such as FFT and FIR as well as matrix multiplies. Acceleration has been added for a wide range of key wireless functions to deliver very high performance in wireless applications.

The ConnX BBE16 DSP is optimized for wireless communication, particularly in LTE and 4G cellular radios and multi-standard broadcast receivers. The high computation requirements of these applications require innovative architectures with a high degree of parallelism and efficient I/O. The ConnX BBE16 DSP meets these needs by combining an 8-way SIMD, 3-issue VLIW processing pipeline with a rich and extensible set of interfaces.

Like all ConnX DSPs, the ConnX BBE16 DSP is fully programmable in C with a vectorizing compiler. Automatic vectorization of scalar C and full support for vector data types allows the development of algorithms without the need to program at the assembly level. Native C operator overloading is supported for natural programming with standard C operators on real and complex vector data types.

Instruction set optimized for DSP

The ConnX BBE16 DSP is an option for the Xtensa LX processor. It adds a highly customized DSP and baseband instruction set.

A wide variety of Load/Store operations support nine different addressing modes with support for 16b/32b scalar and vector data types. Unaligned Load/Stores with masking deliver full bandwidth Loads and Stores for unaligned data. Vector data management is supported with data packing and shifting.

Multiply operations include complex and scalar 18bx18b multiply, multiply-round, multiply-add, and multiply-subtract functions. Complex-number functions include support for conjugate arithmetic and magnitude operations as well as full precision arithmetic and saturated/ rounded outputs. The ConnX BBE16 DSP is capable of performing up to 16 multiplies per operation. BBE16 includes extended precision with guard bits on all register data and full support of double precision data, and 40-bit accumulation on all MAC operations without performance penalty. A wide variety of arithmetic, logical and shift operations are supported for up to eight data words per cycle. There is full support for matrix multiplication with acceleration for OFDM matrix operations.

Our ConnX BBE16 DSPs also support single-cycle radix-4 and radix-8 butterfly operations for efficient high-speed FFT implementations. Support for a single-cycle 4-tap FIR filter with complex taps and single-cycle 16-tap FIR filter with real taps enables efficient filtering operations. Special instructions supporting radix 3/5 FFT are also provided. Symmetric filters on real and complex data at double rate, e.g., 32 real taps/cycle.

Innovative I/O using Ports, Queues, and Lookup interfaces

Connx BBE16 DSPs support custom Ports (general-purpose wire interfaces) and Queues (FIFO) for efficient connection to coprocessors. These custom interfaces can be defined to match the interfaces of existing RTL hardware blocks. Buffered communication between two ConnX BBE16 DSPs or between a ConnX BBE16 DSP and an RTL block can be automatically implemented using Queue interfaces and are fully supported in programming and modeling tools.

Local memories can be connected directly to a ConnX BBE16 DSP using the Lookup interface, bypassing the processor memory bus. This allows efficient implementation of functions that require storage of multiple intermediate datasets. 

Extensible—modify further for your requirements

ConnX BBE16 DSPs can also be modified and extended by defining new instructions, registers, and execution units to augment the existing instruction set. With Cadence, you can choose from a wide range of configuration options.

Supported by a complete set of hardware and software tools

A complete set of tools are available to support ConnX BBE16 DSPs. A comprehensive instruction set simulator (ISS) allows developers to quickly simulate and evaluate performance. The fast, functional TurboSim™ simulator option achieves speeds that are 40 to 80 times faster than the ISS for efficient software development and functional verification. System C and C-based system modeling can aid in full-chip simulations.

The tool set incudes a high-performance C/C++ compiler with automatic vectorization to support the VLIW pipeline in ConnX BBE16 DSPs. This comprehensive tool set also includes the linker, assembler, debugger, profiler, and graphic visualization tools. All major EDA flows are supported. See our Knowledge Center for more details on the tools.

Build Your Own DSPs

Customize your signal processing DSPs

See some interesting ideas, but want something slightly different? That's the beauty of the Cadence Tensilica approach to IP design. From the start, we designed our processor IP to be customizable. We used that same technology to create these innovative baseband DSPs.

Why Cadence?
  • Ultra-low power consumption and size—With optimized DSPs that reduce required system clock frequency
  • Flexibility—A scalable platform to fit all performance, power, and area budgets that can be further customized to meet your needs
  • Reduced development cost and development risk—All programmable in C, backed by a world-class development tool suite and multi-core support
  • Low-risk solution with a large ecosystem—Supports all Tensilica products
We recommend two approaches to get you quickly to the exact product you need:
  • Start with one of our standard ConnX products—Modifying an existing product will save you a lot of design work and effort
  • Start with our Tensilica processor—Starting with a clean slate means you can design everything just the way you'd like it

For digital signal processing (DSP) applications, with unique datapaths, processing requirements, algorithms, and memory requirements, this customization process is often essential to get the smallest, most energy-efficient core possible.

Either way, our automated tools will help you through the design process, making sure the design is correct by construction, and helping you make sure you get the right mix of power, performance, and area. And when you're done, our automated Xtensa processor generator will make sure you get not only the hardware for your new design, but also a complete matching software tool chain.

Accelerate hot spots in applications

You don't have to go to higher MHz to get higher performance. By adding instructions in TIE, our Verilog-like language, you can accelerate hot spots in your applications. You can pump data through our DSPs with up to two 512-bit-wide data load/stores per cycle, or bypass the bus entirely with our unique GPIO and FIFO Queues. Here are some ways you can customize our DSPs:

Data paths

  • The width of data load/store, computation execution, and register files can all be tailored to your specific application

SIMD widths

  • Some applications may greatly benefit from vectorizing computation through a SIMD machine
  • The size of SIMD and vector "strides" can be customized to optimum performance per power/area for the application

Custom instructions

  • Create instructions that perform application-specific tasks
  • Create "incredible performance" for application, reduce instruction memory footprint

Parallel instruction execution

  • VLIW architecture to enable parallel computation of instructions
  • Example: use one instruction to perform load, execute, store

Tools, Software, Libraries for DSPs

Tools, software, libraries—we have what you need to complete your design quickly

For digital signal processing (DSP) applications with unique datapaths, processing requirements, algorithms, and memory requirements, the Cadence customization process is often essential to get the smallest, most energy-efficient core possible. No matter what changes you make, you'll find our tools and software will help you be more efficient.

Hardware design 

For processor designers

Cadence delivers patented, proven tools that automate the process of generating a custom processor or DSP along with matching software tools. These tools have been proven in hundreds of designs. Whether your design is for a simple controller or a complex multi-core DSP design, Cadence has the tools you need to create successful products.

View the complete set of tools for processor designers.

Software design

For software developers

When you need to develop your application software, the Xtensa Software Developer's Toolkit provides a comprehensive collection of code generation and analysis tools that speed the development process. The Cadence Tensilica Eclipse-based Xtensa Xplorer Integrated Development Environment (IDE) serves as the cockpit for the entire development experience.

View the complete set of tools for software developers.

Libraries

Libraries and existing DSP code base support

We do everything we can to make it was easy as possible to port your existing DSP code to our DSPs. Our Xtensa C/C++ Compiler efficiently maps C algorithms to our DSPs, no assembly coding required.

We also provide a range of DSP libraries already tailored to our products, so you can speed your design process.

Literature and Other Resources

Learn more about our baseband processors and DSPs 

Seriously considering using a ConnX DSP in your next SoC design but want to learn more? Here are some things you should explore:

Hardware/Software design tools

Xtensa Processor Developer's Toolkit
Xtensa Software Developer's Toolkit