Home: IP Portfolio > Design IP > Systems/Peripherals IP > Bus and Audio IP

Bus and Audio IP

The peripheral IP bus provides general-purpose interfaces from processors to I/Os generally used in most processor subsystems. These sometimes-forgotten IP binds systems together.

AHBC Arbiter for AHB bus

Cadence® AHBC IP acts as the arbiter for the ARM® AHB™ bus. This IP receives bus requests from masters, and prioritizes the requests using a "round-robin" mechanism or a fixed priority.  Cadence AHBC IP also includes multiplexers for address, data, and control signals between masters and slaves.

 Key Features

  • Fully compliant with ARM AMBA® revision 2.0 32-bit wide data buses for masters
  • Priority is configurable between round robin and fixed, based on master number
  • The number of active masters is controlled by an instantiation parameter and is fixed at hardware build time
  • The number of active slaves is controlled by an instantiation parameter and is controlled at hardware build time
  • Bus granting is re-arbitrated at the end of each burst
  • Slave responses SPLIT and RETRY are supported

AMBA Bridge AHB to APB Bridge IP

Cadence AHB2APB IP interfaces between the AMBA High-Performance Bus (AHB) and the AMBA Peripheral Bus (APB™). It buffers address, control, and data from the AHB, drives the APB peripherals, and returns data and response signals to the AHB. It decodes the address using an internal address map to select the peripheral. This IP is designed to operate when the APB and AHB clocks have the same frequency and phase.

Key Features

  • Interfaces between the AHB and APB (AMBA Specification, Revision 2.0)
  • Provides latching of address, control, and data signals for APB peripherals

Supports

  • APB-compliant slaves and peripherals
  • Peripherals which require additional wait states
  • Peripherals which require byte, half-word, and word accesses on APB bus
  • Big-endian and little-endian modes

APIC Optimizes the performance of interrupt handling

Cadence Programmable Priority Interrupt Controller for ARM ARM7™/ARM9™ (APIC) IP optimizes interrupt-handling performance by reducing latency, and provides prioritized nesting of interrupts.

Key Features

  • Uses the AMBA APB protocol, version 2.0
  • Up to 32 interrupt sources (31 IRQ plus 1 FIQ)
  • Programmable selection for FIQ source
  • Hardware priority encoding for IRQ with up to eight levels of priority
  • Selectable source type: hardware or software
  • All interrupts are maskable
  • Programmable interrupt source types: rising- or falling-edge triggered, or high- or low-level sensitive

ARM7 Cache Controller Interfaces ARM7 processor cores to AHB

The Cadence ARM-based ARM7 Cache Controller IP interfaces ARM7TDMI and ARM7TDMI-S processor cores to an AMBA Advanced High-Performance Bus (AHB). Cache associativity is configurable for direct mapped, 2-way, or 4-way operation. Memory can be partitioned in one or more cacheable regions, with independent read, write, and execute permissions, or can be customized to your requirements

Key Features

  • Compliant with AMBA Spec Rev 2.0
  • Supports ARM7TDMI and ARM7TDMI-S processors
  • Configurable cache size and replacement policy—direct mapped, 2-way, and 4-way set associative
  • Configurable MMU with up to 16 cacheable areas
  • AHB interface supports INCR and WRAP4 burst modes
  • Zero wait states for cache hit, only two-cycle latency for a cache miss or non-cacheable access
  • 8-level write buffer on AHB interface

GPIO Provides up to 32 programmable I/O ports

A Cadence GPIO IP module provides up to 32 programmable I/O ports. Each port can be independently programmed.

Key Features

  • Interfaces to AMBA version 2.0 APB
  • Up to 32 independently programmable I/O ports
  • Each port provides input, output, and output enable for bi-directional I/O pin
  • Each port can be programmed as input or output
  • Each port can be bypassed to or from a separate peripheral device
  • Each port can separately trigger the GPIO interrupt on several event types

I2C Functions as a master or slave in a multi-master, two-wire serial I2C bus

The Cadence I2C IP module is a bus controller that can function as a master or slave in a multi-master, two-wire serial I2C bus.  In master mode, the I2C interface can transmit data to a slave and initiate a transfer to receive data from a slave.  In the optional high-speed mode, the controller can be programmed to up to 3.4Mbps.

Key Features

  • Uses the AMBA APB protocol, version 2.0
  • Uses I2C bus specification version 2.0 (100kHz and 400kHz)
  • Programmable for both normal (100kHz) and fast bus data rates (400kHz)
  • Optional high-speed variant also programmable for up to 3.4Mbps
  • Programmable as either a master or slave interface
  • Programmable to use normal or extended addressing
  • Capable of clock synchronization and bus arbitration
  • Features fully programmable slave response address
  • Provides optional reversible FIFO with parameterizable depth (same register array for receive and transmit)
  • Offers slave monitor mode when set up as master
  • Supports I2C bus hold for slow host service
  • Supports combined format transfers both as master and slave
  • Features slave time-out detection with programmable period
  • Features transfer status interrupts and flags

I2S Configurable single- or multi-channel Inter-IC Sound (I2S) bus interface controller

Cadence I2S-SC IP is a configurable single- or multi-channel Inter-IC Sound (I2S) bus interface controller that combines functions of both transmitter and receiver.  To facilitate the use of the I2S-SC core in various standard bus-based microprocessor systems, various bus wrappers such as AMBA are provided. The I2S-SC IP supports a wide range of transmission parameters that are configurable through SFR registers, thus extending the functionality of the core beyond the I2S standard. 

Key Features

  • Meets Philips Inter-IC Sound Bus Specification
  • Supports various modes : I2S Philips Left or Right Justified , DSP, time-division multiplexing (TDM)
  • Provides two clock domains: host side clock domain, system clock for the I2S channel
  • Offers choice of up to 8 wide-configurable stereo channels and up to 16 channels with TDM support
  • Contains configurable FIFO buffer for transmission channel
  • Interrupts driven by the I2S bus activity events
  • Features handshake interface to external DMA modules
  • Offers extensive core configurability: choose options as needed, or use fully configurable version
  • Provides OCP™-compliant slave interface
  • Offers optional AMBA APB, AMBA AHB, or CoreConnect™ PLB bus wrapper
  • Features transmission FIFO controller
  • Featurse Special Function Registers block (SFR)
  • Single-channel I2S half-duplex transceiver

SPDIF Unidirectional and self-clocking interface for connecting digital audio equipment

Cadence SPDIF Digital Audio Interface Controller IP implements the IEC 60958 interface features (commonly known as Sony/Philips Digital Interface), a unidirectional and self-clocking interface for connecting digital audio equipment using the linear pulse-code modulation (PCM) coded audio samples. The SPDIF can also be used for fast serial non-audio transmission.

Key Features:

  • Available system buses:  AMBA AHB and AMBA APB
  • Receiver/transmitter mode support
  • Data mode capabilities:  sample rate, from 3kHz to 192kHz (with 98MHz SPDIF system clock), 20-/24-bit per sample
  • Integrated APB or AHB slave wrapper to interface with the host AHB or APB controller
  • DMA master handshake interfacing
  • Configurable size of external FIFO
  • Power-safe capability
  • Internal, event-stimulated interrupt request generation with masking capability
  • Synchronization hold in the under-run condition
  • Clock recovery from the SPDIF data stream
  • Variable baud rate

SPI Provides full-duplex, synchronous, serial communication between master and slave

Cadence Serial Peripheral Interface (SPI) IP provides full-duplex, synchronous, and serial communication between master and slave, or other peripheral devices.

Key Features

  • Full-duplex operation with simultaneous receive and transmit
  • Master or slave SPI modes of operation
  • Four wire bus — data RX, data TX, clock, and select
  • Support for multi-master environment - identifies an error condition if more than one master is detected
  • Memory-mapped APB interface with configurable address space
  • Buffered operation with separate transmit and receive FIFOs - the APB can read from the Rx FIFO and write to the Tx FIFO
  • Multiple word transfer per FIFO location
  • Option to use an independent reference clock to decouple APB clock from SPI clock
  •  In master mode, SPI clock can be generated from one of three separate clock sources
  •  Programmable master mode clock frequencies
  • Serial clock with programmable polarity
  • Programmable transmission format
  • FIFO levels available via DUT outputs, or through software-accessible registers
  • FIFO level status can be polled via software or can be interrupt-driven
  • Programmable interrupt generation
  • Up to four external peripheral selects
  • Scan test interface

UART Full duplex asynchronous receiver and transmitter

The Cadence UART IP module is a full-duplex asynchronous receiver and transmitter that supports a wide range of software-programmable baud rates and data formats, and can accommodate automatic parity generation as well as several error detection schemes. The UART IP module is designed for a modem to be connected with both a receive and transmit FIFO, providing a buffer for the CPU. The module is fully compatible with the AMBA APB bus.

Key Features

  • AMBA APB protocol, version 2.0
  • Programmable baud rate generator
  • Configurable receive and transmit FIFOs, with byte, two-byte, or four-byte APB access mechanisms
  •  6, 7, or 8 data bits
  • 1, 1.5, or 2 stop bits
  • Odd, even, space, mark, or no parity
  • Parity, framing, and overflow error detection
  • Line-break generation and detection
  • Automatic echo, local loopback, and remote loopback channel modes
  • Interrupt generation
  • Modem control signals: CTS, RTS, DSR, DTR, RI, and DCD
  • Speed of operation at 200MHz when synthesized using 0.13mm technology
  • IrDA interface