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Advanced Memory IP

Cadence employs some of the best experts in advanced memory so you can get the controllers, PHY, and verification IP you need for the memory in your next system.  We also participate on a variety of standards committees, sharing our IP expertise within the context of evolving standards.  The Cadence® Denali® Memory IP family of solutions addresses both high-performance and low-power applications such as industry-leading 3D-IC (Wide I/O) memory IP and more.

Wide I/O Memory Controller IP Wide I/O controllers supports the latest Wide I/O DRAM standard

Ideal for low-power, wireless, and handheld applications, Cadence Wide I/O Memory Controller IP supports the latest Wide I/O DRAM standard. Wide I/O takes an entirely new approach to power-efficient design. It uses a large number of through-silicon-via (TSV) connections between the SoC and the DRAM to allow a peak memory bandwidth of more than 100Gbps. Wide I/O is projected by manufacturers to use about half the power per bit of LPDDR2 technology. Cadence Design IP for Wide I/O takes our successful low-power DDR Controller IP and ports all of its key features over to our Wide I/O Controller. In addition to supporting the latest Wide I/O features, existing features such as BIST have been expanded to match new properties of Wide I/O devices.

Key Features

  • Supports Wide I/O DRAM memories compliant with JESD229
  • Supports typical 512-bit data interface from SoC to DRAM (4 x 128 bit channels) over TSV at 200MHz
  • Supports 3D-IC chip stacking using direct chip-to-chip contact
  • Supports 2.5D chip stacking using silicon interposer to connect SoC to DRAM
  • Offers priority and quality-of-service (QoS) features
  • Features flexible paging policy including autoprecharge-per-command
  • Features two-stage reordering queue to optimize bandwidth and latency
  • Provides coherent bufferable write completion
  • Includes power-down and self-refresh
  • Offers advanced low-power module that can reduce standby power by 10X
  • Supports single- and multi-port host busses (up to 32 busses with a mix of bus types)
  • Features priority-per-command (AXI4 QoS)
  • BIST algorithm in hardware enables high-speed memory testing and has specific tests for Wide I/O devices