Timer IP

No system can function properly without some kind of clocking. Cadence® Systems and Peripherals IP includes some basic Timing(IP building blocks critical for system operaton.

PWM Can be targeted to virtually any technology

The pulse width modulator (PWM) is a substantially generic design that can be targeted to virtually any technology. The generic nature of its design enables the processor to program the PWM to produce a signal whose period and duty cycle can vary during operation.

Key Features

  • Support for AMBA® APB protocol, version 2.0
  • Programmable module
  • Programmable interrupt
  • Generic design suitable for any technology
  • Parameterizable address and module ID
  • Single clock domain, single edge design
  • Operation at a nominal speed of 133MHz
  • Ability to generate a regular rectangular wave of definable period and duty cycle

RTC Accurate time-of-day keeper plus calendar functionality

The Cadence Real-Time Clock (RTC) IP module tracks time of day to an accuracy of one hundredth of a second (with 100Hz clock; one second with 1Hz clock).  Its calendar functionality keeps track of the day, month, and year. 

Key Features

  • Support for the AMBA APB protocol, version 2.0
  • Complete time-of-day clock: 12/24 hour, hours, minutes, seconds, and hundredths
  • Calendar function: day of week, date of month, month, year, century, leap-year compensation
  • Alarm function: month, date, hour, minute, second, and hundredths resolution
  • Event function: can set interrupt for every roll-over of month, day, hour, minute, second, or hundredth-second
  • Counter clock speed of 100Hz or 1Hz (compile option)
  • Power-down mode with standby pclk clock option
  • Optional byte-addressing mode for APB
  • Time and calendar registers available as core outputs with associated changed indicator


TTC Three independent timers/counters

The Cadence Triple Timer Counter (TTC) IP module provides three independent timer/counter modules that can each be clocked using either the system clock or an externally derived clock. In addition, each counter can independently pre-scale its selected clock.

Key Features

  • Support for the AMBA APB protocol, version 2.0
  • Three independently programmable 16-bit timer/counters
  • Internal or external clock source (one for each timer/counter)
  • 16-bit prescaler, for clock speed selection
  • Three interrupts, one from each timer counter
  • Interrupt generated either on overflow or at regular intervals
  • Interrupt generated when count matches a programmable value
  • Three output waveforms, one from each counter
  • An event timer measures length of each external clock pulse (high or low duration)
  • Counters can be incrementing or decrementing
  • Current value of each count register can be read at any time

WDT Prevents system lockup

Cadence Watchdog Timer (WDT) IP is used to prevent system lockup if software becomes trapped in a deadlock. Under normal operation, the user restarts the watchdog at regular intervals before the timer counts down to zero. If the timer reaches zero and the watchdog is enabled, one or a combination of the following signals is generated: a system reset, an interrupt, or an external signal.

Key Features

  • Uses the AMBA APB version 2.0 protocol
  • On time-out, outputs one or a combination of: system reset, system interrupt, external signal
  • Features variable time-out period - both the countdown rate and the number of cycles to count can be programmed
  • Features variable output signal duration on time-out - you can select the number of clock cycles for which any output signal is active