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SD/SDIO/eMMC IP

Cadence® SD/SDIO/eMMC IP is a family of system-level IP consisting of host controllers and PHY IP. This family of IP addresses a broad range of high-performance as well as low-power requirements for today’s ever-changing design environment, and supports the latest version of Secure Digital (SD) and Embedded Multimedia Memory Card (eMMC) standards. 

Our SD/SDIO/eMMC host controller IP provides connectivity with removable and embedded storage media, including all types of SD and MMC memory cards, and eMMC devices. The covered memory-card density ranges from SDSC through SDHC up to SDXC with a full range of supported speeds: DS, HS, SDR12/25/50/104, DDR50, FD156, and HD312.

 

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Products

Host IP SD/SDIO 3.0/eMMC 4.41 Host Controller, and SD4.0 Host Controller

Cadence SD/SDIO/eMMC Host Controller IP addresses your needs for embedded and removable storage in a wide range of applications. It was designed for low-power as well as high-performance systems, from measurement devices to smartphones, tablets, and cameras.

Our SD/SDIO/eMMC Host Controller IP supports the latest Secure Digital (SD) specification and JEDEC eMMC standard. It offers many configuration options to fit particular design needs in terms of functionality and design constraints. Configurable features include type of DMA, number of slots, internal buffering scheme, speed modes supported, and type of on-­chip memory. Choose from more than 120,000 configurations to create an SD/SDIO/eMMC host controller for your specific requirements.

Our SD/SDIO/eMMC Host Controller IP supports many features for low-power systems, including clock toggling disable. High-performance systems benefit from our advanced DMA engine (ADMA2) with scatter-gather operation. ADMA2 can read data from any number of different-sized locations within system memory without CPU interaction. For designs with silicon area constraints, we offer a single-operation DMA engine option, or you can choose to eliminate the DMA engine entirely.

For systems requiring connection to two or more components, our SD/SDIO/eMMC Host Controller IP supports a multi-slot feature for connecting up to four cards and devices. Any combination of components can be supported, including removable storage or memory cards, embedded eMMC-compliant devices, or extensible I/O such as GPS, Bluetooth®, or 3G cellular radios on SDIO cards.

Fully compatible with the SD host controller standard, our SD/SDIO/eMMC Host Controller IP works seamlessly with native OS drivers embedded in Linux, Microsoft Windows, and other operating systems.

Cadence SD/SDIO 3.0/eMMC 4.41 Host Controller IP supports Default Speed, High Speed, and Ultra High Speed Phase I (SDR12, SDR25, SDR50, SDR104, DDR50) modes for SD/SDIO devices. It also supports Backward Compatible mode, High Speed SDR, and High-­Speed DDR modes for eMMC devices. Cadence SD 4.0 Host Controller IP adds support for the latest Ultra High Speed Phase II (UHS-­II with FD156 and HD312) modes, for unsurpassed throughput with SD memory cards.

 Key Features

  • Supports SD memory, SD I/O cards, and eMMC devices
  • Complies with SD Specification Version 4.0 (Host and PHY) and JEDEC eMMC Standard 4.41
  • Supports Standard (SDSC), High (SDHC), and Extended (SDXC) capacity cards
  • Supports Default Speed, High Speed, Ultra High Speed Phase I, and Ultra High Speed Phase II modes 
  • Features optional SDMA and ADMA2 modules
  • Offers various system side interface options: OCP, ARM® AMBA® AHB™, AMBA AXI™
  • Up to 4 slots available
  • Supports 1-bit, 4-bit, and 8-bit card buses
  • Features ping-pong buffering with block size support up to 2048 bytes
  • Features tuning/retuning logic of sample clock

 

 

Products

SD 3.0/SDIO 3.0/eMMC 4.41 Host Controller IP Multi-slot host controller for SD 3.0 memory, SDIO 3.0 cards, and eMMC 4.41devices
SD 4.0 Host Controller IP Single-slot backward-compatible host controller for SD 4.0 memory cards

PHY IP SD 3.0 UHS-I PHY and UHS-II PHY

Cadence offers separate PHY IP that covers the full range of SD/SDIO/eMMC speeds. Cadence SD 3.0 UHS-I PHY IP supports all SD Ultra High Speed Phase I modes (including SDR104 and DDR50) as well as JEDEC eMMC speeds up to DDR52. For SD 4.0 UHS-II modes, we offer PHY IP from our partner, Silicon Library, Inc.

Our SD 3.0 UHS-I PHY IP facilitates implementation of the SD backend interface for SD/MMC cards and eMMC devices. This IP provides mechanisms that help meet timing requirements for the set of speed modes defined by the SD Physical Layer Specification 3.0 and the JEDEC eMMC Standard 4.41. 

Our SD 3.0 UHS-I PHY IP supports all speed modes defined by SD Physical Layer Specification Version 3.0 and legacy modes defined by SD Physical Layer Specification Version 4.0. Therefore, the SD device can work with Default Speed, High Speed, and Ultra High Speed Phase I in all sub-modes from SDR12 to SDR104 and DDR50. 

Our SD 3.0 UHS-I PHY IP quickly and easily integrates into a system on chip (SoC), and connects seamlessly to our SD/SDIO 3.0/eMMC 4.41 Host Controller IP and SD 4.0 Host Controller IP. 

Silicon Library UHS-II PHY integrates with our SD 4.0 Host Controller IP using a standard LINK-PHY interface. 

Products:

SD 3.0 UHS-I PHY IP PHY for SD/SDIO 3.0/eMMC 4.41 Host Controller, and SD 4.0 Host Controller legacy speed path 
UHS-II PHY from Silicon Library, Inc. SD4.0 UHS-II PHY for SD 4.0 Host Controller UHS-­II speed path. For more information, please visit  www.siliconlib.com/en