Home: IP Portfolio > Design IP > Denali Memory IP > NAND Flash IP


Cadence® NAND Flash IP is a family of system-level IP solutions consisting of NAND Flash Controller IP with compilable ECC and asynchronous, synchronous PHY IP. Our NAND Flash Controller IP addresses a broad range of market requirements, from SSD to basic boot applications including options for low power, reduced gate count, and performance. Our controllers and PHY IP meet all requirements for today’s ever-changing market environment and support all major NAND Flash manufacturers and standards: ONFI 1, ONFi 2, ONFI 3, ONFi 3.4, Toggle 1, Toggle 2, and asynchronous devices. 

Our NAND Flash Controller IP supports all NAND Flash specifications and provides unsurpassed flexibility with the ability to customize a controller to your specific needs. 

Our NAND Flash PHY IP provides a scalable approach for any of your PHY needs, supporting bypass modes and performance capabilities up to DDR800 for most process nodes. Our PHY is available as soft IP, with a targeted delay-locked loop (DLL) for your process and library. 



NAND Flash Controller IP Supports ONFI 3.x/2.x/1.0, Toggle 2/1, and asynchronous memories

Cadence NAND Flash Controller Intellectual Property (IP) provides all the necessary logic required to efficiently control all major NAND Flash devices. 

Supporting all major NAND standards, and providing early support for emerging standards, our NAND Flash Controller IP has many configurable features and input parameters to customize the controller for the specific needs of any application. Support for widely used legacy interfaces is also available. 

Our NAND Flash Controller IP is architected to quickly and easily integrate into any system on chip (SoC) and, when used with the Cadence NAND Flash PHY IP, connects seamlessly from the SoC bus to the I/O drivers in the ASIC I/O pad ring. Client applications access the controller through industry-standard AMBA® AXI3™ or AHB™ interfaces.

Silicon proven, our NAND Flash Controller IP has been extensively validated in many processes and with multiple hardware platforms.

NAND Flash PHY IP Assures correct signal alignment for NAND Flash DDR interface

Cadence NAND Flash PHY IP is an all-digital, soft PHY using a DFI 2.1 interface for its controller-to-PHY interface. Our NAND Flash PHY IP also has a register interface for setup, configuration, and calibration.

Compatible with all major NAND devices, our NAND Flash PHY IP provides a bypass mode to support legacy asynchronous devices within a single interface. The IP also supports ONFI 3.x, 2.x and Toggle 2, 1 interfaces, and legacy asynchronous interfaces.

Architected to quickly and easily integrate into any system on chip (SoC), our NAND Flash PHY IP connects seamlessly to our NAND Flash Controller IP or to third-party NAND Flash controllers that support a modified DFI 2.0 interface. Implemented for the most popular foundries and processes, this IP provides a cost-effective, low-power solution for demanding applications. If you're an SoC integrator, you'll find that our advanced capabilities and support exceed the requirements of high-performance designs and implementations. Our NAND Flash PHY IP supports speeds up to 267MHz and is structured to easily accomodate future clock rate increases. 

Take advantage of an automated design flow with advanced synthesis and static timing analysis (STA) scripts that permit register-transfer level (RTL)-to-placed gates in as few as four hours. 

Based on our proven DDR DRAM PHY design, our NAND Flash PHY IP is silicon-proven and has been extensively validated with multiple hardware platforms.

Software Ease integration with high level software

The Cadence NAND Flash driver reduces your integration effort when implementing a complete NAND Flash subsystem by providing an abstraction layer API that works with our NAND Flash controllers and PHY IP.

Our NAND Flash driver is OS agnostic, and works with any open-source FTL. Based on the Linux 3.0 kernel release, it uses an MTD chip driver and IOCTL interface to access the driver and for device configuration. Code examples for PHY initialization are also supplied.

Our NAND Flash driver exposes all features of our NAND controller IP, including data DMA, command DMA, ECC, and metadata.